Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 09/08/25, 08/30/24 and 08/05/24 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
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Claims 1 and 13 provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 14 of copending Application No. 18/956635 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because claims to the instant application are broader than and fully encompassed by the claims to the co-pending application.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Instant application: 18/794809
Co-pending application: 18/956635
1. A device structure comprising a three-dimensional array of unit cells, wherein each of the unit cells comprises: an access field effect transistor comprising a first horizontally-extending semiconductor channel, a drain region, a first gate dielectric, and a first gate electrode; a memory field effect transistor comprising a second horizontally-extending semiconductor channel, a source region, a second gate dielectric, and a second gate electrode, wherein the second gate dielectric comprises a memory dielectric material having at least two programmable states.
1. A device structure comprising a three-dimensional array of unit cells, wherein each of the unit cells comprises: an access field effect transistor comprising a first horizontally-extending semiconductor channel comprising a first portion of a semiconductor material, a drain region, a first gate dielectric, and a first gate electrode; and a memory field effect transistor comprising a second horizontally-extending semiconductor channel comprising a second portion of the semiconductor material, a second gate dielectric, and a second gate electrode, wherein the second gate dielectric comprises a memory dielectric material having at least two programmable states.
Dependent claim 13 of the instant application corresponds to dependent claim 14 of the co-pending application.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
3.) Claim(s) 1-3, and 13-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (US Pub No.: 2020/0411553A1) and further in view of Lue et al. (US Pub No.: 2012/0020138A1).
Regarding Claim 1, Zhang et al. disclose a device structure comprising a three-dimensional array of unit cells (Three-dimensional array, Abstract and Paragraph 0108), wherein each of the unit cells comprises:
an access field effect transistor (A select gate transistor SG, Paragraph 0105) comprising a first horizontally-extending semiconductor channel (A first semiconductor channel 133, Paragraph 0128; Figure 5A), a drain region (An “active region” of a field effect transistor can be a source region or a drain region, Paragraph 0105), a first gate dielectric (Non-ferroelectric gate dielectric material, Paragraph 0105), and a first gate electrode (A first gate electrode, Paragraph 0107);
a memory field effect transistor (Ferroelectric memory transistor FeFET, Paragraph 0105) comprising a second horizontally-extending semiconductor channel (Second semiconductor channel 135, Paragraphs 0105, 0136; Figure 6A), a source region (As mentioned above an “active region” of a field effect transistor can be a source region or a drain region, Paragraph 0105), a second gate dielectric (A second gate electrode and a second gate dielectric, Paragraphs 0105-0108), and a second gate electrode (A second gate electrode and a second gate dielectric, Paragraphs 0105-0108).
Zhang et al. do not explicitly disclose that the second gate dielectric comprises a memory dielectric material having at least two programmable states. Lue et al. teach of a gate dielectric that comprises a memory dielectric material having at least two programmable states,
(Lue et al. teach of a memory device comprises an array of memory cells each capable of storing multiple bits of data. The memory cells are arranged in memory strings that are connected to a common source line. Each memory cell includes a programmable transistor connected in series with a resistance. The transistor includes a gate dielectric that is switchable between a plurality of different resistance values. The threshold voltage of the transistor changes according to the resistance value of the gate dielectric. Memory states of the memory cells can thus be associated with respective resistance values of the dielectric layer of the transistor, Abstract of Lue et al..
Lue et al. teach that The memory cell can be a first memory cell, and the memory device can further comprise a second memory cell formed above the first memory cell in a lamination direction such that the first and second memory cells are included in a three-dimensional memory array, Paragraph 0017 of Lue et al.. a memory device can comprise an array of memory cells, where at least one of the memory cells comprises a transistor having a first terminal, a second terminal, and a gate structure, the gate structure including a gate dielectric layer. The memory cell also comprises a resistor in series with the gate structure of the transistor. The gate dielectric is switchable between first and second different resistances associated with respective first and second memory states (programmable states), Paragraph 0008 and Claim 1 of Lue et al.. It would have been obvious and well-known to one of ordinary skill in the art before the effective filing date of the claimed invention to enable the teachings of Zhang et al. to have a gate dielectric that comprises a memory dielectric material having at least two programmable states as taught by Zhang et al., because the modification of the structure offers flexibility and helps improve the performance of the device).
With regard to Claim 2, Zhang et al. and Lue et al. disclose the device structure of claim 1, further comprising a doped semiconductor material portion (Active region 134, Paragraph 0117 of Zhang et al.) located between the first horizontally-extending semiconductor channel (First semiconductor channel 133, Paragraphs 0117, 0148-0163 and Figure 8A) and the second horizontally-extending semiconductor channel (Second semiconductor channel 135, Paragraphs 0117, 0148-0163 and Figure 8A).
In regard to Claim 3, Zhang et al. and Lue et al. disclose the device structure of claim 2, wherein the doped semiconductor material portion is in contact with a first sidewall of the first horizontally-extending semiconductor channel and in contact with a first sidewall of the second horizontally-extending semiconductor channel (A second interconnect-level dielectric layer 190 can be deposited over the first interconnect-level dielectric layer 160. The second interconnect-level dielectric layer 190 can include a single dielectric material layer, or may include multiple dielectric material layers. The second interconnect-level dielectric layer 190 includes an interlayer dielectric material such as undoped silicate glass, a doped silicate glass, and/or organosilicate glass, Paragraphs 0148-0163; Figure 8B pf Zhang et al.).
Regarding Claim 13, Zhang et al. and Lue et al. disclose the device structure of claim 1, wherein the second gate dielectric comprises a ferroelectric dielectric material (Ferroelectric material, Paragraphs 0105-0106, 0131-0141 of Zhang et al.).
In regard to Claim 14, Zhang et al. and Lue et al. disclose the device structure of claim 1, wherein:
the drain region (Active region 134 where the second active regions 134 comprise shared source/drain regions of both the first and second field effect transistors, Paragraph 0118 of Zhang et al.) contacts a second sidewall of the first horizontally-extending semiconductor channel (See first semiconductor channel 133, Paragraphs 0128-0129; Figure 5B of Zhang et al.) and has an opposite conductivity type to that of the first horizontally-extending semiconductor channel (Dopants of a second conductivity type that is the opposite of the first conductivity type can be implanted into the line openings in the patterned photoresist layer. Each implanted region of the substrate semiconductor layer 109 constitutes an active region (132, 134, 136). Each active region (132, 134, 136) can include dopants of the second conductivity type at an atomic concentration in a range from 5.0×10.sup.18/cm.sup.3 to 2.0×10.sup.21/cm.sup.3, although lesser and greater dopant concentrations can also be employed, Paragraphs 0117, 0160 of Zhang et al.); and
the source region (See second active region 134, Paragraph 0118 of Zhang et al.) contacts a second sidewall of the second horizontally-extending semiconductor channel (A second semiconductor channel 135, Paragraph 0137, Figure 5B of Zhang et al.) and has an opposite conductivity type to that of the second horizontally-extending semiconductor channel (Dopants of a second conductivity type that is the opposite of the first conductivity type can be implanted into the line openings in the patterned photoresist layer. Each implanted region of the substrate semiconductor layer 109 constitutes an active region (132, 134, 136). Each active region (132, 134, 136) can include dopants of the second conductivity type at an atomic concentration in a range from 5.0×10.sup.18/cm.sup.3 to 2.0×10.sup.21/cm.sup.3, although lesser and greater dopant concentrations can also be employed, Paragraphs 0117, 0160 of Zhang et al.).
With regard to Claim 15, Zhang et al. and Lue et al. disclose the device structure of claim 1, wherein the three-dimensional array of the unit cells comprises rows of respective unit cells arranged along a second horizontal direction that is different from the first horizontal direction, columns of respective unit cells arranged along the first horizontal direction, and vertical stacks of respective unit cells arranged along a vertical direction (The active regions (132, 134, 136) are laterally spaced apart along the first horizontal direction. In one embodiment, a neighboring pair of ferroelectric memory unit cells can be laterally spaced apart along the first horizontal direction hd1, and can have a pair of mirror image layouts with a plane of symmetry that is perpendicular to the first horizontal direction hd1. In this case, a repetition unit including a third active region 136, a second active region 134, a first active region 132, a second active region 134, and a third active region 136 can be repeated along the first horizontal direction hd1 between each neighboring pair of dielectric isolation structures 12 such that first active regions 132 are shared between neighboring pairs of repetition units. In this configuration, the first active regions 132 comprise the source regions of adjacent first field effect transistors SG, the second active regions 134 comprise shared source/drain regions of both the first and second field effect transistors, and the third active region 136 comprise drain regions of the second field effect transistors FeFET, Paragraph 0118 of Zhang et al.).
Regarding Claim 16, Zhang et al. and Lue et al. disclose the device structure of claim 15, further comprising:
a two-dimensional array of vertical bit lines (See respective bit lines BL, Paragraph 0106 and Figure 1A of Zhang et al.), wherein each of the vertical bit lines contacts a set of the drain regions located within a respective vertical stack of unit cells (The first active regions 132 comprise the source regions of adjacent first field effect transistors SG, the second active regions 134 comprise shared source/drain regions of both the first and second field effect transistors, and the third active region 136 comprise drain regions of the second field effect transistors FeFET. The source regions 132 are electrically connected to the source lines SL, the drain regions 136 are connected to the bit lines BL, Paragraph 0118 of Zhang et al.); and
a two-dimensional array of vertical source lines (Respective source lines SL, Paragraph 0106, Figure 1A of Zhang et al.), wherein each of the vertical source lines contacts a set of the source regions located within a respective vertical stack of unit cells (Each first active region (e.g., source region) of the ferroelectric memory unit cells UC can be connected to a respective source line SL, which is an electrically conductive line that laterally extends along a horizontal direction. In the circuit of FIG. 1A, all unit cells (e.g., memory cells) UC share the same source line SL. In the circuit of FIG. 1B, the unit cells UC in the same column share the same source line SL, but unit cells in different columns are connected to different source lines SL. Another active region (e.g., drain region which may correspond to the second or third active region) of the ferroelectric memory unit cells UC can be connected to a respective bit line BL, which is an electrically conductive line and may laterally extend along a direction parallel to the lengthwise direction of the bit lines BL, Paragraph 0106 of Zhang et al.).
4.) Allowable Subject Matter
i.)
Claims 4-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
ii.)
Claims 17-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
In regard to independent Claim 17, the closest prior-art of record fails to teach or reasonably disclose the combination of the limitations to the claim that includes, “A method of forming a device structure, comprising:
forming vertically alternating stacks of in-process horizontally-extending semiconductor rails and in-process horizontally-extending sacrificial rails, wherein each of the vertically alternating stacks laterally extends along a first horizontal direction, and the vertically alternating stacks are laterally spaced apart from each other along a second horizontal direction by lateral isolation trenches including uniform width portions and laterally bulging portions;
patterning the vertically alternating stacks, wherein patterned portions of the vertically alternating stacks comprise a three-dimensional array of horizontally-extending semiconductor rails each containing a respective first horizontally-extending semiconductor channel, a respective doped semiconductor material portion which is a respective one of the doped semiconductor material portions, and a second horizontally-extending semiconductor channel;
depositing a second gate dielectric material and a second gate electrode material around the second horizontally-extending semiconductor channels;
forming a one-dimensional array of bridges-encircling cavities such that each two-dimensional array of doped semiconductor material portions arranged along directions that are perpendicular to the first horizontal direction is exposed to a respective one of the bridges-encircling cavities; and
isotropically etching the first gate electrode material and the second gate electrode material around the one-dimensional array of bridges-encircling cavities, wherein remaining portions of the first gate electrode material comprise a two-dimensional array of first word lines, and remaining portions of the second gate electrode material comprise a two-dimensional array of second word lines.”
Dependent Claims 18-20 are also allowed due to their dependence on allowed independent claim 17.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PRITHAM DAVID PRABHAKHER whose telephone number is (571)270-1128. The examiner can normally be reached Monday to Friday 8:00 am to 5:00 pm EST.
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Pritham David Prabhakher
Patent Examiner
Pritham.Prabhakher@uspto.gov
/PRITHAM D PRABHAKHER/Primary Examiner, Art Unit 2638
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