Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Examiner’s Comments
The circuitry recited throughout he claims is drawn to the structure of a microprocessor that performs the logical functions as recited in said claims, using program code as recited throughout the claims.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-39 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-19 of U.S. Patent No. 11432069. Although the claims at issue are not identical, they are not patentably distinct from each other because the application claims a broader version of the same system claimed by the patent with obvious variations as taught by the cited prior art below.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
The following claims 1,3-14,16-27,29-39, is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Clark et al (US 10547927 B1).
As per claim 1, Clark discloses a system, comprising: a circuitry configured to:
generate a mid component and a side component from a left channel and a right channel of an audio signal (fig. 6, MID and SIDE outputs of mid-side block);
generate a hyper mid component by removing spectral energy of the side component from spectral energy of the mid component (it is removed via the M-S function as output by the Mid Side stage, where the subtraction removes spectral energy ); and
generate a left output channel and a right output channel using the hyper mid component (the generation of Lout and Rout is based on M-S, and also based on the filtering applied to the mid signal, and also based on the synchronization required to generate leftout and rightout signals per fig. 6).
As per claim 14, the system of the claim 1 rejection requires a non-transitory computer readable medium comprising stored program code, the program code when executed by at least one processor configures the at least one processor to:
generate a mid component and a side component from a left channel and a right channel of an audio signal;
generate a hyper mid component by removing spectral energy of the side component from spectral energy of the mid component (it is removed via the M-S function as output by the Mid Side stage, where the subtraction removes spectral energy );
generate a left output channel and a right output channel using the hyper mid component (per claim 1 rejection).
As per claim 27, the claim 1 and 14 rejections disclose a method, comprising, by a circuitry: generating a mid component and a side component from a left channel and a right channel of an audio signal; generating a hyper mid component by removing spectral energy of the side component from spectral energy of the mid component (it is removed via the M-S function as output by the Mid Side stage, where the subtraction removes spectral energy ); and generating a left output channel and a right output channel using the hyper mid component (per claim 1 and 14 rejections).
As per claims 2,15,28, (CANCELLED) the system of claim 1, wherein the circuitry is configured to decorrelate the mid component from the side component by removing spectral energy of the side component from spectral energy of the mid component (it is removed via the M-S function and or the filtering applied to the mid signal per fig. 6).
As per claims 3,16,29, the system of claim 1, wherein the circuitry is further configured to: generate a residual mid component by further decorrelating the mid component from the hyper mid component (DRC further decorrelates the hyper mid component output from the band pass filter) ; and
wherein the left output channel and the right output channel are further generated using the residual mid component (per Lout and Rout).
As per claims 4,17,30, the system of claim l, wherein the circuitry is further configured to: filter subbands of the hyper mid component (the DRC stages in fig. 6); and
wherein the left output channel and the right output channel are generated using the filtered subbands of the hyper mid component (outputs of the DRC stages are used to create Lou and Rout).
As per claims 5,18,31, the system of claim 4, wherein each of the subbands of the hyper mid component includes a set of critical bands (the critical bands are the bands that are read into and recognized by the processor per the output of the band pass filter stages).
As per claims 6,19,32, the system of claim l, wherein the circuitry is further configured to:
generate a hyper side component by further decorrelating the side component from the mid component (output of the first filter receiving the side signal in fig. 3);
generate a residual side component by further decorrelating the side component from the hyper side component (para 5 the outputs of either of these stages: the side pathway is delayed by the same amount of delay as is induced in the mid pathway (either processed or unprocessed). In another embodiment, a phase correction network is employed in the side signal pathway to match the phase distortion induced in the mid signal pathway. ) ;
generate the left and right output channels using the hyper side component and the residual side component (Lout and Rout as per fig. 3 and 6).
As per claims 7,20,33, the system of claim 6, wherein the circuitry is further configured to:
filter subbands of the hyper side component (301 and 302 filter the subbands for all subsequent processing stages, including generation of then hyper side component);
filter subbands of the residual side component (301 and 302 filter the subbands for all subsequent processing stages, including generation of then hyper side component); and
generate the left and right output channels using the filtered subbands of the hyper side component (per the lout and rout).
As per claims 8,21,34 the system of claim l, wherein the circuitry is further configured to apply crosstalk processing to the audio signal, the crosstalk processing including one of a crosstalk cancellation or a crosstalk simulation (the phase processing applied to the audio signals in para 4, to match phase distortion is crosstalk processing because properly phase aligned signals have less crosstalk when combined on the output side).
As per claims 9,22,35 the system of claim 8, wherein the circuitry is further configured to filter the hyper mid component to compensate for spectral defects caused by the crosstalk processing ( the side pathway is delayed by the same amount of delay as is induced in the mid pathway (either processed or unprocessed) per para 5, in view of the crosstalk processing in fig. 4).
As per claims 10,23,36 the system of claim 8, wherein the circuitry is further configured to: generate a residual mid component by further decorrelating the mid component from the hyper mid component (based on the drc filtering 201 in fig. 3);
and filter the residual mid component to compensate for spectral defects caused by the crosstalk processing (para. 5: a phase correction network is employed in the unprocessed mid signal pathway to match the phase distortion induced in the mid processing pathway. ).
As per claims 11,24,37, the system of claim 8, wherein the circuitry is further configured to filter the mid component to compensate for spectral defects caused by the crosstalk processing (para 5: para. 5: a phase correction network is employed in the unprocessed mid signal pathway to match the phase distortion induced in the mid processing pathway).
As per claims 12,25,38, the system of claim 8, wherein the circuitry is further configured to:
generate a hyper side component by further decorrelating the side component from the mid component (any of the phase corrections cited in the claim 10 and 11 rejections will generate signals with aligned phases, which functions to decorrelate the channels from each other when combined to form the L and R signals );
generate a residual side component by further decorrelating the side component from the hyper side component (any of the phase corrections cited in the claim 10 and 11 rejections will generate signals with aligned phases, which functions to decorrelate the channels from each other when combined to form the L and R signals );
filter the hyper side component to compensate for spectral defects caused by the crosstalk processing (any of the phase corrections cited in the claim 10 and 11 rejections will generate signals with aligned phases, which functions to decorrelate the channels from each other when combined to form the L and R signals, further noting any phase changes to one signal must be compensated for in other signals used in the same processing blocks in order to synchronize the signals for processing );.
As per claims 13,26,39, the system of claim 8, wherein the circuitry is further configured to filter the side component to compensate for spectral defects caused by the crosstalk processing (any of the phase corrections cited in the claim 10 and 11 rejections will generate signals with aligned phases, which functions to decorrelate the channels from each other when combined to form the L and R signals, further noting any phase changes to one signal must be compensated for in other signals used in the same processing blocks in order to synchronize the signals for processing ).
Response to Arguments
The submitted arguments have been considered but are moot in view of the new grounds of rejection.
As per applicant’s argument that the prior art Clark does not disclose removing spectral energy as per the claim 1,14 and 27 rejections, the examiner notes the cited processing which produces the M-S signal from the Mid Side Block in Fig. 6, is a subtraction and will remove spectral energy from the mid signal being used by said mid side block. Additionally, the previously cited multi band DRC processing on the Mid signal is in dependence upon the side signal as they are processed together in the Mid Side stage, as such the dynamic range of each must be set in a manner in order to obtain a meaningful M-S signal. Hence the spectral energy of the MID is reduced per the Side via both in the DRC stage and also via the M-S signal output form the Mid Side Stage.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDER KRZYSTAN whose telephone number is 571-272-7498, and whose email address is alexander.krzystan@uspto.gov
The examiner can usually be reached on m-f 7:30-4:00 est.
If attempts to reach the examiner by telephone or email are unsuccessful, the examiner’s supervisor, Fan Tsang can be reached on (571) 272-7547.
The fax phone numbers for the organization where this application or proceeding is assigned are 571-273-8300 for regular communications and 571-273-8300 for After Final communications.
/ALEXANDER KRZYSTAN/Primary Examiner, Art Unit 2653
Examiner Alexander Krzystan
October 13, 2026
