Reissue
For reissue applications filed on or after September 16, 2012, all references to 35 U.S.C. 251 and 37 CFR 1.172, 1.175, and 3.73 are to the current provisions.
Status of Claims
Amended patent claims 1-7 and new claims 8-34 are pending.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 9 and 10 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement.
The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Specifically, new claims 9 and 10 recite the back surface of a semiconductor element is planarized through a “removing step” or “an exposing step” of a portion of the protective layer. However, the disclosure of US 10,600,932, hereinafter ‘the ‘932 patent, describes planarization is achieved only through the more specific step of grinding.
For example, the ‘932 patent discloses:
“the protective layer 13 is grinded (step S04). After grinding the protective layer 13 to level with the micro-sized optoelectronic semiconductor elements 12, the grinding step is still continued until the residuals R on the back surface 121 of each of the micro-sized optoelectronic semiconductor elements 12 and the back surface 121 are removed to expose a new surface 122…a grinding machine is provided to grind the object from the top surface 131 of the protective layer 13 to the matrix substrate 11. When the grinding machine reaches the back surface 121 of the micro-sized optoelectronic semiconductor element 12, the grinding process is still continued. This step can not only remove the residuals R on the back surface 121 but also planarize the back surface 121. The grinding process continues to remove a part of each micro-sized optoelectronic semiconductor element 12 until a new surface 122 of each micro-sized optoelectronic semiconductor element 12 away from the matrix substrate 11 is exposed.” See col.6, lines 10-30.
There is no description or embodiment where the back surface of a semiconductor element is planarized by the more generic methods of “removing” or “exposing,” as recited in claims 9 and 10. These more generic methods would encompass methods such as, inter alia, chemical etching, laser ablation, and other mechanical means. Because the ‘932 patent discloses only a step of grinding that accomplishes planarizing the semiconductor, claims 9 and 10 fail to comply with the written description requirement.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-4, 11, 12, and 26 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
With respect to claims 2 and 3, the phrase “the grinding step is to remove the buffer layer and a part of the non-doped layer” renders the claim vague and indefinite when considered with respect to claim 1 which states that grinding removes the protective layer and a residual. It is suggested to amend claim 2 to clarify that the grinding step additionally removes the buffer layer and a part of the non-doped layer.
Similarly, in claim 4 the phrase “the grinding step is to planarize the back surface” renders the claim vague and indefinite for the reasons set forth above. It is suggested to amend claim 4 to clarify that the grinding step further or additionally planarizes the back surface.
As to claims 11-12, the phrase “an upper surface of the back surface” in line 2 is indefinite. It is suggested to delete “an upper surface of” as the semiconductor elements cannot have both an upper surface and a back surface. Notably the specification describes only a back surface.
With respect to claim 26, recitation of a thickness of the non-doped layer of “less than 1.8 µm” is confusing with respect to claim 1 from which the claim ultimately depends. Neither claim 1 nor claim 25 require grinding of the non-doped layer. However, the claimed thickness occurs only after grinding. Thus, claims 25 and 26 should be amended to depend from claim 2.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 4, 8-10, 13, 14, 19, 21-24, 27-30, 33, and 34 is/are rejected under 35 U.S.C. 103 as being unpatentable over Applicant’s Admission of the Prior Art (hereinafter AAPA) in view of US 2009/0115042 to Koyanagi (hereinafter Koyanagi) and US 2016/0056055 to Ko et al. (hereinafter Ko).
With respect to claims 1, 4, 8-10, 22-24, 27-30, 33, and 34, AAPA (Description of Related Art; col.1, lines 25-67) teaches a known method of manufacturing micro optoelectronic semiconductor devices includes epitaxially growing GaN diodes on a temporary substrate followed by transferring a plurality of the diodes to a silicon matrix substrate. The temporary substrate is subsequently removed via LLO, leaving a residue of gallium metal on the diode. The conventional method of removing the residue is by using a chemical such as an acid. AAPA does not teach the matrix substrate comprises a circuit, that at least one electrode of each semiconductor device is connected with the circuit, forming a protective layer covering the semiconductor elements, or grinding the protective layer so as to remove the residual and the back surface to expose a new surface.
PNG
media_image1.png
428
602
media_image1.png
Greyscale
Koyanagi discloses it was known when manufacturing micro semiconductor elements to attach the semiconductors 13 to a substrate 11 having a circuit layer 12 thereon, and electrically connect the electrodes on the semiconductors to the electrodes on the substrate. See Figure 1; paras [0015, 0224]. It would have been obvious to one of ordinary skill in the art to provide a circuit on the substrate disclosed by AAPA, and connect the semiconductor to the circuit using electrodes in the known manner, as doing so permits the diode to operate according to the desired function of the circuit.
Koyanagi discloses forming a protective layer 14 around each semiconductor 13. Additionally, the protective layer is added to the top surface of the semiconductor. See Figure 1 (c). The protective layer and back surface of the semiconductor is mechanically polished (i.e. grinding) to remove the protective layer and planarize the semiconductor, exposing a new layer level with a surface of the adjacent protective layer. See Figure 1 (d); paras [0028, 0073, 0076, 0225-0227]. The protective layer is an insulating adhesive, such as an epoxy. See paras [0284-0285]. Further, the protective layer is disclosed to provide mechanical and electrical stability to the semiconductors arranged on the substrate (para [0023]) and planarization unifies the size/height of the semiconductors (para [0028]).
PNG
media_image2.png
214
506
media_image2.png
Greyscale
Ko teaches a method of manufacturing semiconductors devices wherein semiconductor dies 130 are electrically connected to a substrate 120 through redistribution layer 112 and electrodes 131 (para [0035]) and the entire array is covered with an encapsulant 140. See Figure 2I; para [0037]. Ko specifically states that the “encapsulant 140 may, for example, be formed to entirely cover the second surface 110b of the interposer 110 and the semiconductor die 130” (para [0037]). Thus, although shown in Figure 2I to only cover the side of die 130, the encapsulant 140 may entirely cover the semiconductor die. See also Figure 6J, illustrating the encapsulant 450 entirely covering die 440. Ko discloses that “[s]uch covering may then, for example if exposure of the semiconductor die 130 is desired, by followed by back grinding and/or etching or otherwise thinning (if needed) to allow the first surface 130a of the semiconductor die 130 to be exposed from the encapsulant 140.” See para [0037]. As shown in the Figures, the semiconductor element is leveled with a surface of the adjacent protective layer/encapsulant. The encapsulant is disclosed by Ko to protect the die from environmental and electrical damage and may be epoxy. See paras [0034, 0037, 0129].
It would have been obvious to completely cover the micro optoelectronic semiconductor devices of AAPA with a protective layer/encapsulant as disclosed by Ko and Koyanagi in order to provide mechanical stability and protection from environmental or electrical damage. Further, it would have been obvious to grind down the encapsulant from the back surface of the dies, in order to expose and thin them to a uniform height in the manner disclosed by Ko and Koyanagi. Doing so would necessarily remove any gallium residue remaining on the dies.
As to claim 13, Ko teaches that it was known in the art at the time of the invention to use photodiodes as a light-receiving element in a sensor array. See para [0003]. It would have been obvious to one of ordinary skill in the art to employ the modified micro LEDs of AAPA in a sensor since this is a known utility and one would have yielded predictable results. See MPEP 2143 I C.
As to claim 14, AAPA discloses the micro optoelectronic devices are LEDs. See col.1, lines 45-50.
With respect to claim 19, AAPA discloses that a plurality of dies are transferred to the target substrate. While AAPA is silent as to how the dies are arranged, at the very least they would be considered to be in an “irregular shape” if not arranged in a particular order.
As to claim 21, AAPA is silent as to the spacing of adjacent semiconductor elements. However, as the elements are micro optoelectronic devices and as one would have been motivated to maximize the number of devices on a substrate, it would have been obvious to optimize the spacing/pitch to be within the claimed range for improved economics of production and handling.
Claim(s) 2, 3, 5-7, 20, 25, 26, 31, and 32 is/are rejected under 35 U.S.C. 103 as being unpatentable over AAPA, Koyanagi, and Ko as applied to claim 1 above, and further in view of US 2017/0062683 to Chen et al. (hereinafter Chen).
With respect to claims 2, 3, 25, and 26, AAPA is silent as to arrangement of the layers within the micro LED semiconductor elements. Chen discloses a micro LED device comprising a p-type semiconductor layer 122, a light-emitting layer 123, an n-type semiconductor layer 124, a non-doped layer 121 (para [0073]), and a buffer layer (last line of para [0073]). It would have been obvious to use the LED semiconductor structure of Chen in the invention of AAPA, as Chen discloses growth of a p-n diode layer on a substrate is
PNG
media_image3.png
214
324
media_image3.png
Greyscale
known and conventional. See paras [0070-0071]. As to the thickness of the non-doped layer after grinding, Koyanagi and Ko each teach that the semiconductors may be thinned to the desired thickness by grinding. See Koyanagi, paras [0028, 0055, 0251]; Ko, paras [0037, 0110]. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Thus, it is deemed obvious to optimize the process of the combination to achieve a semiconductor die having the desired thickness for the particular use.
As to claims 5-7, AAPA as modified by Koyanagi and Ko is silent to a substrate on the plurality of semiconductor elements. However, Chen discloses micro LEDs like that of AAPA that may additionally have a microlens array on top of the array of semiconductor elements. See Figure 22B; para [0155]. It would have been obvious to place a microlens array on top of the diode array of the combination, as microlens arrays are commonly used in LED technology for creating uniform illumination. As to the relative refractive indexes of the protective layer, protective substrate, and lenses, one of ordinary skill in the art of LED technology would have been motivated to maintain the refractive indexes of each of these layer to be index matched in order to avoid light refracting and reflecting thus achieving a single beam of light.
With respect to claim 20, AAPA is silent as to the length of the micro-sized semiconductor elements. However, Chen teaches micro devices generally have a size of 1 to 100 µm. See para [0062]. One of ordinary skill in the art would understand the micro devices of AAPA to fall within the same range.
As to claims 31 and 32, the combination of AAPA with Koyanagi and Ko discloses an LED having a horizontal structure, where the electrodes are on the same side of the semiconductor element. Chen however teaches that micro-LEDs may also have a vertical configuration wherein electrodes 150,160 are disposed on opposite sides of the structure. See Figure 1B. As vertical micro-LEDs are generally known to have superior brightness and energy efficiency, it would have been obvious to manufacture vertical LEDs using the method of modified AAPA.
Claim(s) 15, 28, and 30-33 is/are rejected under 35 U.S.C. 103 as being unpatentable over AAPA, Koyanagi, and Ko as applied to claim 1 above, and further in view of US 2017/0365755 to Chu (hereinafter Chu).
AAPA, as modified by Koyanagi and Ko, discloses the manufacture of micro optoelectronic devices but does not disclose they are configured to be mounted on a VR or AR display device. Chu teaches it was known in the art to mount micro LEDs in a head mounted display, VR display, and AR display. See para [0003]. As the micro LEDs of AAPA would have small size and high resolution, one would have found it obvious to use them in displays requiring these parameters, such as VR and AR displays.
Claim(s) 16-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over AAPA, Koyanagi, and Ko as applied to claim 1 above, and further in view of US 2017/0301724 to Lee (hereinafter Lee).
AAPA as modified by Koyanagi and Ko is silent to the matrix circuit including a plurality of active elements or a plurality of interlaced data and scan lines. Lee discloses a manufacture method of a display substrate wherein the substrate 10 includes TFTs 20 on one side of the substrate and micro-LEDs 20 on the other side of the device, such that each TFT switches ON/OFF a corresponding micro-LED. See paras [0026-0027]; Figure 2. Further, Lee teaches the substrate has plural “data lines intersected with scan lines to define a plurality of pixel regions. Each of the pixel regions comprising a displaying unit and a switch device…” See para [0008]. As a display is a common use of micro-LEDs due to their brightness and high resolution, it would have been obvious to mount the micro LEDs of AAPA on a TFT substrate having data and scan lines in the manner disclosed by Lee.
Allowable Subject Matter
Claims 11 and 12 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The closest prior art of record, Koyanagi and Ko, do not teach or suggest an upper surface of the protective layer is on a different level than the back surface of at least one of the semiconductor elements. In Koyanagi and Ko, after the grinding/polishing step, the protective layer and the back surface of the semiconductor elements are at the same height and there is no motivation to grind only part of the protective layer or semiconductor element such that the protective layer is on a different level than the back surface of at least one of the semiconductor elements.
Conclusion
Applicant is reminded of the continuing obligation under 37 CFR 1.178(b), to timely apprise the Office of any prior or concurrent proceeding in which Patent No. 10,600,932 is or was involved. These proceedings would include any trial before the Patent Trial and Appeal Board, interferences, reissues, reexaminations, supplemental examinations, and litigation.
Applicant is further reminded of the continuing obligation under 37 CFR 1.56, to timely apprise the Office of any information which is material to patentability of the claims under consideration in this reissue application.
These obligations rest with each individual associated with the filing and prosecution of this application for reissue. See also MPEP §§ 1404, 1442.01 and 1442.04.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's
supervisor Patricia Engle can be reached on 571-272-6660. The fax phone number for
the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be
obtained from Patent Center. Unpublished application information in Patent Center is
available to registered users. To file and manage patent submissions in Patent Center,
visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for
information about filing in DOCX format. For additional questions, contact the Electronic
Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a
USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or
571-272-1000.
/ELIZABETH L MCKANE/Specialist, Art Unit 3991
Conferees:
/LEE E SANDERSON/Reexamination Specialist, Art Unit 3991
/Patricia L Engle/SPRS, Art Unit 3991
Prosecution Insights