DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Miscellaneous
The Applicant has cancelled non-elected claims 1-8 and added new claims 21-28; therefore, only claims 9-28 remain for this Office Action.
Election/Restrictions
Claims 1-8 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected Group I, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 1/20/2026.
Applicant's election with traverse of Group II in the reply filed on 1/20/2026 is acknowledged. The traversal is on the ground(s) that there would be no serious burden on the Examiner. This is not found persuasive because as noted within the previous Office Action, Group II did not require the size constraints nor the plurality of controllers required by Group I.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 9-13 and 21-25 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Iwanczuk et al. (US 6,069,489).
In regards to claim 9, Iwanczuk discloses of a method comprising: receiving configuration data; and programming the configuration data into configuration memory of programmable logic circuity of an integrated circuit device using one or more 1-bit wide data registers (for example see Figs 2, 6-7, 17 and Column 5 Lines 34-54, Column 9 Lines 15-32, 48-67, Column 10 Lines 1-6, Column 18 Lines 12-44 and Column 19 Lines 18-23).
In regards to claim 10, Iwanczuk discloses of the method of claim 9, wherein programming the configuration data comprises sending the configuration data through an address register coupled to the one or more 1-bit wide data registers (for example see Figs 2, 6-7, 17 and Column 5 Lines 34-54, Column 9 Lines 15-32, 48-67, Column 10 Lines 1-6, Column 18 Lines 12-44 and Column 19 Lines 18-23).
In regards to claim 11, Iwanczuk discloses of the method of claim 10, wherein programming the configuration data comprises sending the configuration data through the address register to an addressed region of programmable logic circuitry connected to the address register via the one or more 1-bit wide data registers (for example see Figs 2, 6-7, 17 and Column 5 Lines 34-54, Column 9 Lines 15-32, 48-67, Column 10 Lines 1-6, Column 18 Lines 12-44 and Column 19 Lines 18-23).
In regards to claim 12, Iwanczuk discloses of the method of claim 9, wherein programming the configuration data comprises sending the configuration data through an address register coupled to a first array of the 1-bit wide data registers to provide data in and a second array of data registers to provide data out (for example see Figs 2, 6-7, 17 and Column 5 Lines 34-54, Column 9 Lines 15-32, 48-67, Column 10 Lines 1-6, Column 18 Lines 12-44 and Column 19 Lines 18-23).
In regards to claim 13, Iwanczuk discloses of the method of claim 9, wherein programming the configuration data comprises performing partial reconfiguration of a region of the programmable logic circuity of the integrated circuit device (for example see Column 2 Lines 52-58, Column 3 Lines 26-39 and Column 4 Lines 1-19).
In regards to claim 21, Iwanczuk discloses of a method comprising: receiving data associated with an integrated circuit device; and programming the data into a memory of the integrated circuit device using one or more 1- bit wide data registers (for example see Figs 2, 6-7, 17 and Column 5 Lines 34-54, Column 9 Lines 15-32, 48-67, Column 10 Lines 1-6, Column 18 Lines 12-44 and Column 19 Lines 18-23).
In regards to claim 22, Iwanczuk discloses of the method of claim 21, wherein programming the data comprises sending the data through an address register coupled to the one or more 1-bit wide data registers (for example see Figs 2, 6-7, 17 and Column 5 Lines 34-54, Column 9 Lines 15-32, 48-67, Column 10 Lines 1-6, Column 18 Lines 12-44 and Column 19 Lines 18-23).
In regards to claim 23, Iwanczuk discloses of the method of claim 22, wherein programming the data comprises sending the data through the address register to an addressed region of programmable logic circuitry connected to the address register via the one or more 1-bit wide data registers (for example see Figs 2, 6-7, 17 and Column 5 Lines 34-54, Column 9 Lines 15-32, 48-67, Column 10 Lines 1-6, Column 18 Lines 12-44 and Column 19 Lines 18-23).
In regards to claim 24, Iwanczuk discloses of the method of claim 21, wherein programming the data comprises sending the data through an address register coupled to a first array of the 1-bit wide data registers to provide data in and a second array of data registers to provide data out (for example see Figs 2, 6-7, 17 and Column 5 Lines 34-54, Column 9 Lines 15-32, 48-67, Column 10 Lines 1-6, Column 18 Lines 12-44 and Column 19 Lines 18-23).
In regards to claim 25, Iwanczuk discloses of the method of claim 21, wherein programming the data comprises performing partial reconfiguration of a region of programmable logic circuity of the integrated circuit device (for example see Column 2 Lines 52-58, Column 3 Lines 26-39 and Column 4 Lines 1-19).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 28 is rejected under 35 U.S.C. 103 as being unpatentable over Iwanczuk et al. (US 6,069,489) in view of How et al. (US 2016/0049941).
In regards to claim 28, Iwanczuk discloses of the method of claim 25 as found within the explanation above, wherein the integrated circuit device comprises a field programmable gate array (FPGA).
However, Iwanczuk does not explicitly disclose of wherein the integrated circuit device comprises an application-specific integrated circuit.
One having ordinary skill in the art would readily recognize alternative programmable logic devices may be used for this integrated circuit device, including application-specific integrated circuits (ASICs). Furthermore, How also discloses of programmable circuits and/or FPGAs terms applicable to other suitable circuits such as ASICs (see Paragraphs 0057, 0065)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the integrated circuit being application-specific as taught by How to alternatively provide specific logic resources to achieve a specific function.
Allowable Subject Matter
Claims 16-20 are allowed. The following is an examiner’s statement of reasons for allowance:
In regards to claim 16, the prior art does not disclose of a method comprising: performing an initial configuration of programmable logic circuitry of an integrated circuit device; and subsequently performing partial reconfiguration of a region of the programmable logic circuitry using a write-only operation, nor would it have been obvious to one of ordinary skill in the art to do so. Claims 17-20 are also allowed as being dependent on claim 16.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claims 14-15 and 26-27 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
In regards to claim 14, the prior art does not disclose of the method of claim 13, wherein performing the partial reconfiguration of the region of the programmable logic circuity of the integrated circuit device comprises a write-only operation that avoids a read-modify-write, nor would it have been obvious to one of ordinary skill in the art to do so.
In regards to claim 15, the prior art does not disclose of the method of claim 9, wherein programming the configuration data comprises performing single-event update (SEU) detection for a region of the programmable logic circuity of the integrated circuit device that comprises less than 1% of all of the programmable logic circuity of the integrated circuit device, nor would it have been obvious to one of ordinary skill in the art to do so.
In regards to claim 26, the prior art does not disclose of the method of claim 25, wherein performing the partial reconfiguration of the region of the programmable logic circuity of the integrated circuit device comprises a write- only operation that avoids a read-modify-write, nor would it have been obvious to one of ordinary skill in the art to do so.
In regards to claim 27, the prior art does not disclose of the method of claim 25, wherein programming the data comprises performing single-event update (SEU) detection for the region of the programmable logic circuity of the integrated circuit device that comprises less than 1% of all of the programmable logic circuity of the integrated circuit device, nor would it have been obvious to one of ordinary skill in the art to do so.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jason M Crawford whose telephone number is (571)272-6004. The examiner can normally be reached Mon-Fri 6:00am-3:00pm.
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/JASON M CRAWFORD/Primary Examiner, Art Unit 2844