DETAILED ACTION
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 08/05/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 5, 9, 11, 13, 16, 17 and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Farazmand et al US 20170212563.
Regarding claim 1, Farazmand teaches a device comprising an accelerator (see figure 2A, device 10 comprising GPU 12), the accelerator including:
an interface to receive a frequency control signal from a processor (interface connecting GPU 12 and processor 16, see para 0070, Processor 16 may then output information indicating the performance level of GPU 12);
a circuit to process data based at least in part on a data processing command from the processor (circuit including shader core 36, see para 0036, GPU 12 may also be configured to execute commands that are issued to GPU 12 by processor 16, also see para 0046, the commands that GPU 12 is to execute are executed by shader core 36); and
a control circuit to set a frequency of the circuit based at least in part on the frequency control signal from the processor (controller 30, see para 0068, controller 30 may determine whether to increase or decrease the frequency of the clock signal. Controller 30 may increase the clock rate if controller 30 determines that a higher performance level (e.g., higher clock rate) is needed to execute the commands within the time period than the current clock rate for timely execution, also see para 0069, controller 30 may determine the performance level based on information received from processor 16 that indicates the performance level).
Regarding claim 2, Farazmand further teaches the interface is configured to receive the frequency control signal from a software executing on the processor (see para 0075, processor 16 may execute power management module 32… In one example of frequency management performed by power management module 32, power management module 32 may determine a performance level needed by GPU 12).
Regarding claim 5, Farazmand further teaches the frequency control signal is based at least in part on one of a first workload of the accelerator or a first implementation of the accelerator (see para 0078, based on the statistics of the workload of GPU 12, power management module 32 may continuously determine the frequency of the clock signal).
Regarding claim 9, Farazmand further teaches the control circuit applies the frequency control signal to the data processing command (see para 0067, To ensure that GPU 12 is able to execute the submitted commands within the set time period, controller 30 may adjust the frequency (i.e., clock rate) and/or voltage of the clock signal).
Regarding claim 11, Farazmand teaches a method, comprising:
receiving a frequency control signal from a processor at a control circuit of an accelerator, the processor external to the accelerator (processor 16 and controller 30 of GPU 12, see para 0070, Processor 16 may then output information indicating the performance level of GPU 12); and
applying the frequency control signal to a circuit of the accelerator by the control circuit, the circuit configured to process data based at least in part on a data processing command from the processor (see para 0068, controller 30 may determine whether to increase or decrease the frequency of the clock signal. Controller 30 may increase the clock rate if controller 30 determines that a higher performance level (e.g., higher clock rate) is needed to execute the commands within the time period than the current clock rate for timely execution, also see para 0069, controller 30 may determine the performance level based on information received from processor 16 that indicates the performance level).
Regarding claim 13, Farazmand further teaches applying the frequency control signal to the circuit of the accelerator by the control circuit includes applying the frequency control signal to the circuit of the accelerator by the control circuit for the data processing command (see para 0067, To ensure that GPU 12 is able to execute the submitted commands within the set time period, controller 30 may adjust the frequency (i.e., clock rate) and/or voltage of the clock signal).
Regarding claim 16, Farazmand teaches a system, comprising a non-transitory storage medium, the non-transitory storage medium having stored thereon instructions that, when executed by a machine (see para 0030, system memory 14 may be a computer-readable storage medium having instructions stored thereon that, when executed, cause one or more processors (e.g., processor 16 and GPU 12) to perform various functions), result in:
receiving a frequency control signal from a processor at a control circuit of an accelerator, the processor external to the accelerator (processor 16 and controller 30 of GPU 12, see para 0070, Processor 16 may then output information indicating the performance level of GPU 12); and
applying the frequency control signal to a circuit of the accelerator by the control circuit, the circuit configured to process data based at least in part on a data processing command from the processor (see para 0068, controller 30 may determine whether to increase or decrease the frequency of the clock signal. Controller 30 may increase the clock rate if controller 30 determines that a higher performance level (e.g., higher clock rate) is needed to execute the commands within the time period than the current clock rate for timely execution, also see para 0069, controller 30 may determine the performance level based on information received from processor 16 that indicates the performance level).
Regarding claims 17 and 19, please refer to the rejection of claims 5 and 9 since the claimed subject matter is substantially similar.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-4 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Farzamand as applied to claims above, and further in view of Idgunji et al US 20200050920.
Regarding claim 3, Farazmand teaches all the features with respect to claim 1 as outlined above.
But Farazmand fails to teach a Proportional Integrator Derivative (PID) controller to generate an internal frequency control signal for the accelerator sent to the control circuit.
However, Idgunji teaches a PID controlled to generate an internal frequency control signal for the accelerator sent to the control circuit (see figure 4, PID controller 440, see para 0105, The output W(t) of the PID controller 440 is provided to the frequency/voltage controller 122 for adjusting the operating frequency and/or voltage of the processing system (e.g., GPU 102)).
Therefore, it would have been obvious to modify the accelerator of Farazmand and further incorporate the PID controller.
The motivation for doing so is to allow fixed or self-tuned parameters for the accelerator as taught by Idgunji (see para 0108).
Regarding claim 4, Farazmand further teaches the control circuit applies the frequency control signal (see para 0068, controller 30 may determine whether to increase or decrease the frequency of the clock signal. Controller 30 may increase the clock rate if controller 30 determines that a higher performance level (e.g., higher clock rate) is needed to execute the commands within the time period than the current clock rate for timely execution).
Regarding claim 12, Farazmand teaches all the features with respect to claim 11 as outlined above.
But, Farazmand fails to teach generating an internal frequency control signal at a Proportional Integrator Derivative (PID) controller of the accelerator; and sending the internal frequency control signal from the PID controller to the control circuit; and applying the frequency control signal to the circuit of the accelerator by the control circuit includes overriding the internal frequency control signal with the frequency control signal.
However, Idgunji teaches generating an internal frequency control signal at a Proportional Integrator Derivative (PID) controller of the accelerator; and sending the internal frequency control signal from the PID controller to the control circuit (see figure 4, PID controller 440, see para 0105, The output W(t) of the PID controller 440 is provided to the frequency/voltage controller 122 for adjusting the operating frequency and/or voltage of the processing system (e.g., GPU 102)); and applying the frequency control signal to the circuit of the accelerator by the control circuit includes overriding the internal frequency control signal with the frequency control signal (see para 0078, the learning system 150 may modify the control parameters of the frequency/voltage control system 122 so that the error is reduced faster and/or reduce overshoots when moving the frequency and/or voltage. The learning system 150 may receive the error, the current power used by the GPU 102 and/or predicted power from the processors 116 e.g. overriding internal PID control).
Therefore, it would have been obvious to modify the accelerator of Farazmand and further incorporate the PID controller and overriding of the PID controller.
The motivation for doing so is to allow fixed or self-tuned parameters for the accelerator as taught by Idgunji (see para 0108).
Claims 6-8 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Farzamand as applied to claims above, and further in view of Hutton et al US 20230119235.
Regarding claim 6, Farazmand teaches all the features with respect to claim 5 as outlined above.
But Farzmand fails to teach the frequency control signal is further based at least in part on one of a second workload of a second accelerator or a second implementation of the second accelerator.
However, Hutton teaches controlling a frequency of an accelerator based on multiple workloads of multiple accelerator including at least in part on one of a second workload of a second accelerator or a second implementation of the second accelerator (see figure 4, multiple accelerators 414, see para 0066, adjusting voltage/frequency setpoints may involve determining a synchronization point in the performance of the parallel-partitioned workload, and adjusting a performance speed of each of the chips to reach the synchronization point at a common time. The synchronization point may be a point in the workflow at which all of the chips are expected to have completed about an amount of the workload).
Therefore, it would have been obvious to modify the frequency control system of Farazmand and further incorporate controlling the frequency based on workloads of multiple accelerators.
The motivation for doing so is to optimize the performance of the system having multiple accelerators as taught by Hutton (see para 0057).
Regarding claim 7, Farazmand teaches all the features with respect to claim 5 as outlined above.
Farazmand further teaches the workload of the accelerator includes a dimensionality of a data to be processed using the accelerator or a first number of vectors of the data to be processed by the accelerator (see figure 3 and para 0086, Work items 54A and 54B represent two of the work items of workgroup 52. Kernel 50 in FIG. 3 is shown as a three-dimensional structure, similar to the three-dimensional structures used in OpenCL and other software frameworks).
But Farzamand fails to teach the frequency control signal is further based at least in part on one of a second workload of a second accelerator or a second implementation of the second accelerator.
However, Hutton teaches controlling a frequency of an accelerator based on multiple workloads of multiple accelerator including at least in part on one of a second workload of a second accelerator or a second implementation of the second accelerator (see figure 4, multiple accelerators 414, see para 0066, adjusting voltage/frequency setpoints may involve determining a synchronization point in the performance of the parallel-partitioned workload, and adjusting a performance speed of each of the chips to reach the synchronization point at a common time. The synchronization point may be a point in the workflow at which all of the chips are expected to have completed about an amount of the workload).
Therefore, it would have been obvious to modify the frequency control system of Farazmand and further incorporate controlling the frequency based on workloads of multiple accelerators.
The motivation for doing so is to optimize the performance of the system having multiple accelerators as taught by Hutton (see para 0057).
Regarding claim 8, Farazmand teaches all the features with respect to claim 5 as outlined above.
But Farazmand fails to teach the frequency control signal is further based at least in part on one of a second workload of a second accelerator or a second implementation of the second accelerator, the frequency control signal coordinating the accelerator and the second accelerator.
However, Hutton teaches controlling a frequency of an accelerator based on multiple workloads of multiple accelerator including at least in part on one of a second workload of a second accelerator or a second implementation of the second accelerator, the frequency control coordinating the accelerator and the second accelerator (see figure 4, multiple accelerators 414, see para 0066, adjusting voltage/frequency setpoints may involve determining a synchronization point in the performance of the parallel-partitioned workload, and adjusting a performance speed of each of the chips to reach the synchronization point at a common time. The synchronization point may be a point in the workflow at which all of the chips are expected to have completed about an amount of the workload).
Therefore, it would have been obvious to modify the frequency control system of Farazmand and further incorporate controlling the frequency based on workloads of multiple accelerators.
The motivation for doing so is to optimize the performance of the system having multiple accelerators as taught by Hutton (see para 0057).
Regarding claim 18, please refer to the rejection of claim 6 above since the claimed subject matter is substantially similar.
Claims 10, 14-15 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Farzamand as applied to claims above, and further in view of Iwata et al US 20210091756
Regarding claim 10, Farazmand teaches all the features with respect to claim 1 as outlined above.
But Farazmand fails to teach the frequency control signal de-asserts a second frequency control signal.
However, Iwata teaches a frequency control signal de-asserts a second frequency control signal (see figure 2 shows that the frequency-divider enable signal de-asserts the frequency division ratio signal feeding into the frequency divider 2, also see para 0042).
Therefore, it would have been obvious to modify the frequency control system of Farazmand and further incorporate multiple frequency control signals.
The motivation for doing so is to enable/disable frequency control in different time periods as taught by Iwata (see the abstract).
Regarding claim 14, Farazmand teaches all the features with respect to claim 11 as outlined above.
But Farazmand fails to teach overriding a second frequency control signal by the control circuit based at least in part on the frequency control signal.
However, Iwara teaches overriding a second frequency control signal by the control circuit based at least in part on the frequency control signal (see figure 2 shows that the frequency-divider enable signal overriding the frequency division ratio signal feeding into the frequency divider 2, also see para 0042).
Therefore, it would have been obvious to modify the frequency control system of Farazmand and further incorporate multiple frequency control signals.
The motivation for doing so is to enable/disable frequency control in different time periods as taught by Iwata (see the abstract).
Regarding claim 15, please refer to the rejection of claim 10 above since the claimed subject matter is substantially similar.
Regarding claim 20, please refer to the rejection of claim 14 since the claimed subject matter is substantially similar.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Narayanaswamy et al US 20240094796 discloses techniques to optimize performance of a processor group based on workload factors
Alla et al US 20210200255 discloses adjusting clock rate of a GPU based on different workload types
Nijasure et al US 20210157639 discloses workload-based clock adjustment at a processing unit
Oh et al US 20140063026 discloses adjusting a frequency and operating voltage of the GPU based on the 3D input data
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/PHONG H DANG/Primary Examiner, Art Unit 2184