DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
No information disclosure statement (IDS) was filed before the mailing date of this office action.
Response to Arguments
Applicant’s arguments, see Remarks, filed 07/28/2026, with respect to the rejection(s) of independent claims 9, 16 and 20 under 35 USC § 103 have been fully considered but are moot because of the new ground of rejection based on a newly found prior art, Morita, US 11669252.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 6, 11 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over US-PGPUB No. 2009/0102643 A1 to Haid, US-PGPUB No. 2013/0016832 A1 to Yamashita, and further in view of USPAT No. 11669252 B1 to Morita et al. (hereinafter “Morita”)
Regarding claim 1:
Haid discloses:
A control chip (see Fig. 8, Secure Control Chip 94), comprising:
a control circuit (¶03: “a data processing circuit”) …
a sensor (see Fig. 8, secure sensor 92) …
a transmission path (see Fig. 8, the transmission path between secure controller 94 and secure sensor 92) …
However, Haid does not explicitly disclose the following limitations taught by Yamashita:
[a control circuit], configured to encrypt output information by a key to generate encrypted information (Yamashita, ¶44: “… to encrypt data, the security chip (security device) 20 … generates a scramble key … The security chip 20 … generates the encrypted data by encrypting the encryption target data using the encryption unit 24, and transmits the encrypted data to the host chip 10.”), and configured to output the encrypted information to [a sensor] (¶44: “… generates the encrypted data … and transmits the encrypted data to the host chip 10.”) via [a transmission path] (¶24: “The security chip 20 is connected with a host chip 10 via a bus line or serial line,”), wherein the transmission path and the sensor are outside the control chip (see Fig. 2, the serial line and host chip 10 are outside security chip 20);
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention, to modify the teachings of Haid to incorporate the functionality of the security chip to generate encrypted data and transmit to the host chip, as disclosed by Yamashita, such modification would enable the system to prevent information leakage.
The combination of Haid and Yamashita does not explicitly teach the following limitation taught by Morita:
wherein the key is updated (Marita, see Fig. 10, steps S1002: “Key Removal Instruction (CPU → Cryptographic Operation Circuit)”, S1003: “Remove Encryption Key to be Updated” and S1004: “Execute Key Registration Process”. See also col 9, lines 60-61: “FIG. 10 shows an example of a key update process. The key update process is started at predetermined timing. The predetermined timing may be periodic, a predefined date and time, timing designated by the user, or another timing.”) by a circuit inside the control chip (Marita, see Fig. 1, Encryption Circuit 113B inside Cryptographic Operation Circuit 113, col 5, lines 35-36: “The cryptographic operation circuit 113 is, for example, an FPGA.”), based on a rule recorded in the control chip (Marita, see Fig. 1, Key Information 113A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the teachings of the combination of Haid and Yamashita to incorporate the system architecture to include an encryption circuit in an FPGA (chip) (integrated encryption engine) for updating an encryption key, as disclosed by Morita, such modification of incorporating an integrated encryption engine provides a uniform security level of encryption algorithms which can secure the security of an entire system.
Regarding claim 6:
Haid discloses:
A sensing chip (see Fig. 8, Sensing chip module 92), comprising:
a sensor (¶03: “a chip module including a sensor,”) …
a transmission path (see Fig. 8, the transmission path between secure controller 94 and secure sensor 92) …
However, Haid does not explicitly disclose the following limitations taught by Yamashita:
[a sensor], configured to encrypt output information by a key to generate encrypted information (Yamashita, ¶44: “… to encrypt data, the security chip (security device) 20 … generates a scramble key … The security chip 20 … generates the encrypted data by encrypting the encryption target data using the encryption unit 24, and transmits the encrypted data to the host chip 10.”), and outputs the encrypted information to a control circuit (Yamashita, ¶44: “… generates the encrypted data … and transmits the encrypted data to the host chip 10.”) via [a transmission path] (Yamashita, ¶24: “The security chip 20 is connected with a host chip 10 via a bus line or serial line,”), wherein the control circuit and the transmission path are outside the sensing chip (Yamashita, see Fig. 2, the serial line and host chip 10 are outside security chip 20);
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention, to modify the teachings of Haid to incorporate the functionality of the security chip to generate encrypted data and transmit to the host chip, as disclosed by Yamashita, such modification would enable the system to prevent information leakage.
The combination of Haid and Yamashita does not explicitly teach the following limitation taught by Morita:
wherein the key is updated (Marita, see Fig. 10, steps S1002: “Key Removal Instruction (CPU → Cryptographic Operation Circuit)”, S1003: “Remove Encryption Key to be Updated” and S1004: “Execute Key Registration Process”. See also col 9, lines 60-61: “FIG. 10 shows an example of a key update process. The key update process is started at predetermined timing. The predetermined timing may be periodic, a predefined date and time, timing designated by the user, or another timing.”) by a circuit inside the [sensing] chip (Marita, see Fig. 1, Encryption Circuit 113B inside Cryptographic Operation Circuit 113, col 5, lines 35-36: “The cryptographic operation circuit 113 is, for example, an FPGA.”), based on a rule recorded in the [sensing] chip (Marita, see Fig. 1, Key Information 113A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the teachings of the combination of Haid and Yamashita to incorporate the system architecture to include an encryption circuit in an FPGA (chip) (integrated encryption engine) for updating an encryption key, as disclosed by Morita, such modification of incorporating an integrated encryption engine provides a uniform security level of encryption algorithms which can secure the security of an entire system.
Regarding claim 11:
Haid discloses:
A sensing system control method (¶70: “methods for protecting a chip module comprising a sensor and/or actuator and a data processing circuit connected between an input/output interface and a sensor and/or actuator …”), applied to a sensing system comprising a sensor in a sensing chip (see Fig. 8, sensor chip module 92), a transmission path (see Fig. 8, see the communication path between sensor chip module 92 and control chip 94) and a control circuit in a control chip (see Fig. 8, control chip 94), comprising:
wherein the sensing chip and the control chip are independent from each other (see Fig. 8, sensor chip module 92 and control chip 94 are independent chips), and the transmission path is outside the sensing chip and the control chip (see Fig. 8, the transmission path indicated to be outside both chips).
Haid does not explicitly disclose the following limitations taught by Yamashita:
encrypting first output information using a first key by the control circuit to generate first encrypted information (Yamashita, ¶44: “The security chip 20 … generates the encrypted data by encrypting the encryption target data using the encryption unit 24, …”);
outputting the first encrypted information to the transmission path by the control circuit (Yamashita, ¶44: “The security chip 20 … transmits the encrypted data to the host chip 10.”, see Fig. 2 for the transmission path); and
receiving the first encrypted information by the sensor via the transmission path (Yamashita, see Fig. 4, scrambled cipher data Y1 received by host chip 10);
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention, to modify the teachings of Haid to incorporate the functionality of the security chip to generate encrypted data and transmit to the host chip, as disclosed by Yamashita, such modification would enable the system to prevent information leakage.
The combination of Haid and Yamashita does not explicitly teach the following limitation taught by Morita:
wherein the first key is updated (Marita, see Fig. 10, steps S1002: “Key Removal Instruction (CPU → Cryptographic Operation Circuit)”, S1003: “Remove Encryption Key to be Updated” and S1004: “Execute Key Registration Process”. See also col 9, lines 60-61: “FIG. 10 shows an example of a key update process. The key update process is started at predetermined timing. The predetermined timing may be periodic, a predefined date and time, timing designated by the user, or another timing.”) by a circuit inside the control chip (Marita, see Fig. 1, Encryption Circuit 113B inside Cryptographic Operation Circuit 113, col 5, lines 35-36: “The cryptographic operation circuit 113 is, for example, an FPGA.”), based on a rule recorded in the control chip (Marita, see Fig. 1, Key Information 113A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the teachings of the combination of Haid and Yamashita to incorporate the system architecture to include an encryption circuit in an FPGA (chip) (integrated encryption engine) for updating an encryption key, as disclosed by Morita, such modification of incorporating an integrated encryption engine provides a uniform security level of encryption algorithms which can secure the security of an entire system.
Regarding claim 16:
The combination of Haid, Yamashita and Morita discloses:
The sensing system control method of claim 11, further comprising:
encrypting second output information using a second key by the sensor to generate second encrypted information (Yamashita, ¶74: “… the host chip 10 generates a second scramble key S2 by performing the XOR operation on the random number R2 and the second authentication code A2 (s). Then the host chip 10 generates scrambled data X2 … by performing the XOR operation on the encryption target data D2 and the scramble key S22, and transmits the scrambled data X2 to the security chip 20 …”, see Fig. 4); and
outputting the second encrypted information to the control circuit via the transmission path (Yamashita, ¶74: “… the host chip 10 generates scrambled data X2 … and transmits the scrambled data X2 to the security chip 20 …”, see Fig. 4).
The same motivation which is applied to claim 11 with respect to Yamashita applies to claim 16.
Claims 2-4, 7-9, 12-14 and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Haid, Yamashita, Morita, and further in view of US-PGPUB No. 2013/0002609 A1 to Lim et al. (hereinafter “Lim”)
Regarding claim 2:
The combination of Haid, Yamashita and Morita discloses the control chip of claim 1, but does not explicitly teach the following limitation taught by Lim:
wherein the control chip is configured to control an optical navigation system and the sensor is an optical sensor (Lim, ¶21: “… the optical sensor and the microcontroller may be components of the optical navigation device 102 … the microcontroller communicates data to the CPU via a data bus.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the system architecture of the combination of Haid, Yamashita and Morita by incorporating an optical navigation sensor, and incorporating the functionality of the microcontroller to control the optical navigation system, as disclosed by Lim, such modification would enable the system to output two-dimensional movement information that represents a two-dimensional movement of a surface relative to a sensor array, and is used to move a cursor on a display of a corresponding computing device.
Regarding claim 3:
The combination of Haid, Yamashita and Morita discloses the control chip of claim 1, but does not explicitly teach the following limitation taught by Lim:
wherein the output information is information for setting operation parameters of the sensor (Lim, ¶38-39: “Resolution adjustment can be accomplished by having the microcontroller monitor the reported movement information and changing the sensor resolution setting as required by the application. … the optical navigation sensor 202 monitors the native movement information and changes the resolution of the sensor array 128 automatically.”), wherein the operation parameters include addresses or values of registers (Lim, ¶40: “… the resolution of the sensor array 128 is controlled by setting register values.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the system architecture of the combination of Haid, Yamashita and Morita by incorporating an optical navigation sensor, and incorporating the functionality of the microcontroller to control the optical navigation system, as disclosed by Lim, such modification would enable the system to output two-dimensional movement information that represents a two-dimensional movement of a surface relative to a sensor array, and is used to move a cursor on a display of a corresponding computing device.
Regarding claim 4:
The combination of Haid, Yamashita and Morita discloses the control chip of claim 1, but does not explicitly teach the following limitation taught by Lim:
wherein the output information comprises accessing addresses (Lim, see Table 1, Optical Navigation Sensor Register Addresses 0x64 to 0x6b).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the system architecture of the combination of Haid, Yamashita and Morita by incorporating an optical navigation sensor, and incorporating the functionality of the microcontroller to control the optical navigation system, as disclosed by Lim, such modification would enable the system to output two-dimensional movement information that represents a two-dimensional movement of a surface relative to a sensor array, and is used to move a cursor on a display of a corresponding computing device.
Regarding claim 7:
The combination of Haid, Yamashita and Morita discloses the sensing chip of claim 6, but does not explicitly teach the following limitation taught by Lim:
wherein the output information comprises sensing data generated by the sensor (Lim, ¶22: “the optical navigation sensor 202 generates movement data, referred to herein as "native" movement information and provides the native movement information to the microcontroller 204.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the system architecture of the combination of Haid, Yamashita and Morita by incorporating an optical navigation sensor, and incorporating the functionality of the microcontroller to control the optical navigation system, as disclosed by Lim, such modification would enable the system to output two-dimensional movement information that represents a two-dimensional movement of a surface relative to a sensor array, and is used to move a cursor on a display of a corresponding computing device.
Regarding claim 8:
The combination of Haid, Yamashita and Morita discloses the sensing chip of claim 6, but does not explicitly teach the following limitation taught by Lim:
wherein the sensing chip is for an optical navigation system and the sensor is an optical sensor (Lim, ¶21: “… the optical sensor and the microcontroller may be components of the optical navigation device 102 … the microcontroller communicates data to the CPU via a data bus.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the system architecture of the combination of Haid, Yamashita and Morita by incorporating an optical navigation sensor, and incorporating the functionality of the microcontroller to control the optical navigation system, as disclosed by Lim, such modification would enable the system to output two-dimensional movement information that represents a two-dimensional movement of a surface relative to a sensor array, and is used to move a cursor on a display of a corresponding computing device.
Regarding claim 9:
The combination of Haid, Yamashita and Morita discloses the sensing chip of claim 8, but does not explicitly teach the following limitation taught by Lim:
wherein the output information comprises motion data generated by the optical sensor (Lim, ¶22: “… the optical navigation sensor 202 generates movement data,”).
The same motivation which is applied to claim 8 with respect to Lim applies to claim 9.
Regarding claim 12:
The combination of Haid, Yamashita and Morita discloses the sensing system control method of claim 11, but does not explicitly teach the following limitation taught by Lim:
wherein the sensing system is an optical navigation system and the sensor is an optical sensor (Lim, ¶21: “… the optical sensor and the microcontroller may be components of the optical navigation device 102 … the microcontroller communicates data to the CPU via a data bus.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the system architecture of the combination of Haid, Yamashita and Morita by incorporating an optical navigation sensor, and incorporating the functionality of the microcontroller to control the optical navigation system, as disclosed by Lim, such modification would enable the system to output two-dimensional movement information that represents a two-dimensional movement of a surface relative to a sensor array, and is used to move a cursor on a display of a corresponding computing device.
Regarding claim 13:
The combination of Haid, Yamashita and Morita discloses the sensing system control method of claim 11, but does not explicitly teach the following limitation taught by Lim:
wherein the first output information is information for setting operation parameters of the sensor (Lim, ¶38-39: “Resolution adjustment can be accomplished by having the microcontroller monitor the reported movement information and changing the sensor resolution setting as required by the application. … the optical navigation sensor 202 monitors the native movement information and changes the resolution of the sensor array 128 automatically.”), wherein the operation parameters include addresses or values of registers (Lim, ¶40: “… the resolution of the sensor array 128 is controlled by setting register values.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the system architecture of the combination of Haid, Yamashita and Morita by incorporating an optical navigation sensor, and incorporating the functionality of the microcontroller to control the optical navigation system, as disclosed by Lim, such modification would enable the system to output two-dimensional movement information that represents a two-dimensional movement of a surface relative to a sensor array, and is used to move a cursor on a display of a corresponding computing device.
Regarding claim 14:
The combination of Haid, Yamashita and Morita discloses the sensing system control method of claim 11, but does not explicitly teach the following limitation taught by Lim:
wherein the first output information comprises accessing addresses (Lim, see Table 1, Optical Navigation Sensor Register Addresses 0x64 to 0x6b).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the system architecture of the combination of Haid, Yamashita and Morita by incorporating an optical navigation sensor, and incorporating the functionality of the microcontroller to control the optical navigation system, as disclosed by Lim, such modification would enable the system to output two-dimensional movement information that represents a two-dimensional movement of a surface relative to a sensor array, and is used to move a cursor on a display of a corresponding computing device.
Regarding claim 17:
The combination of Haid, Yamashita and Morita discloses the sensing system control method of claim 16, but does not explicitly teach the following limitation taught by Lim:
wherein the second output information comprises sensing data generated by the sensor (Lim, ¶22: “… the optical navigation sensor 202 generates movement data,”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the system architecture of the combination of Haid, Yamashita and Morita by incorporating an optical navigation sensor, and incorporating the functionality of the microcontroller to control the optical navigation system, as disclosed by Lim, such modification would enable the system to output two-dimensional movement information that represents a two-dimensional movement of a surface relative to a sensor array, and is used to move a cursor on a display of a corresponding computing device.
Regarding claim 18:
The combination of Haid, Yamashita and Morita discloses the sensing system control method of claim 16, but does not explicitly teach the following limitation taught by Lim:
wherein the sensing system is an optical navigation system and the sensor is an optical sensor (Lim, ¶21: “… the optical sensor and the microcontroller may be components of the optical navigation device 102 … the microcontroller communicates data to the CPU via a data bus.”), wherein the second output information comprises motion data generated by the optical sensor (Lim, ¶22: “… the optical navigation sensor 202 generates movement data,”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the system architecture of the combination of Haid, Yamashita and Morita by incorporating an optical navigation sensor, and incorporating the functionality of the microcontroller to control the optical navigation system, as disclosed by Lim, such modification would enable the system to output two-dimensional movement information that represents a two-dimensional movement of a surface relative to a sensor array, and is used to move a cursor on a display of a corresponding computing device.
Claims 5, 10, 15 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Haid, Yamashita, Morita, and further in view of US-PGPUB No. 2020/0382953 A1 to Li
Regarding claim 5:
The combination of Haid, Yamashita and Morita discloses the control chip of claim 1, but does not explicitly teach the following limitation taught by Li:
wherein the key is recorded in a storage device inside the control chip (Li, ¶63: “… the first terminal private key is stored in the first terminal security chip …”), wherein the control chip does not output the key and does not receive the key from outwards, after the key has been recorded in the storage device (Li, ¶63: “… the first terminal private key is stored in the first terminal security chip and cannot be obtained by the external terminal, thereby ensuring the security of the second random number.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the system architecture of the combination of Haid, Yamashita and Morita to incorporate the functionality of the method to store the terminal private key in a first terminal security chip, as disclosed by Li, such modification would enable the system to ensure the security of the key by preventing external access.
Regarding claim 10:
The combination of Haid, Yamashita and Morita discloses the sensing chip of claim 6,, but does not explicitly teach the following limitation taught by Li:
wherein the key is recorded in a storage device inside the sensing chip, wherein the sensing chip does not output the key and does not receive the key from outwards, after the key has been recorded in the storage device (Li, ¶63: “… the first terminal private key is stored in the first terminal security chip and cannot be obtained by the external terminal, thereby ensuring the security of the second random number.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the system architecture of the combination of Haid, Yamashita and Morita to incorporate the functionality of the method to store the terminal private key in a first terminal security chip, as disclosed by Li, such modification would enable the system to ensure the security of the key by preventing external access.
Regarding claim 15:
The combination of Haid, Yamashita and Morita discloses the sensing system control method of claim 11, but does not explicitly teach the following limitation taught by Li:
wherein the first key is recorded in a storage device inside the control chip, wherein the control chip does not output the first key and does not receive the first key from outwards, after the first key has been recorded in the storage device (Li, ¶63: “… the first terminal private key is stored in the first terminal security chip and cannot be obtained by the external terminal, thereby ensuring the security of the second random number.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the system architecture of the combination of Haid, Yamashita and Morita to incorporate the functionality of the method to store the terminal private key in a first terminal security chip, as disclosed by Li, such modification would enable the system to ensure the security of the key by preventing external access.
Regarding claim 20:
The combination of Haid, Yamashita and Morita discloses the sensing system control method of claim 16, but does not explicitly teach the following limitation taught by Li:
wherein the second key is recorded in a storage device inside the sensing chip, wherein the sensing chip does not output the second key and does not receive the second key from outwards, after the second key has been recorded in the storage device (Li, ¶63: “… the first terminal private key is stored in the first terminal security chip and cannot be obtained by the external terminal, thereby ensuring the security of the second random number.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the system architecture of the combination of Haid, Yamashita and Morita to incorporate the functionality of the method to store the terminal private key in a first terminal security chip, as disclosed by Li, such modification would enable the system to ensure the security of the key by preventing external access.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Haid, Yamashita, Morita, and further in view of US-PGPUB No. 2025/0385788 A1 to Shin
Regarding claim 19:
The combination of Haid, Yamashita and Morita discloses the sensing system control method of claim 16, but does not explicitly teach the following limitation taught by Shin:
further comprising:
storing the second key to the sensor while manufacturing the sensing chip (Shin, ¶03: “in a process of manufacturing a chip or chipset to be mounted on a semiconductor device, a value of the key may be fused into a one-time programmable (OTP) memory included as a component of the semiconductor device.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the system architecture of the combination of Haid, Yamashita and Morita to incorporate the functionality of the method to fuse a key in a semiconductor device capable of executing security software including a security application into a one-time programmable (OTP) memory included as a component of the semiconductor device while manufacturing a chip, as disclosed by Shin, such modification would enable the system to generate a more secure key encryption key (KEK).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHIAS HABTEGEORGIS whose telephone number is (571)272-1916. The examiner can normally be reached M-F 8am-5pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William R. Korzuch can be reached at (571)272-7589. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MATTHIAS HABTEGEORGIS/Examiner, Art Unit 2491
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