Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination
2. A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 06/08/2026 has been entered.
DETAILED ACTION
3. This Office Action is in response to the filing with the office dated 06/08/2026.
Claims 1 and 6 have been amended. Claims 5 and 10 have been cancelled. Claims 1 and 6 are independent Claims. Claims 1-4 and 6-9 are presented in this office action.
Priority
4. Applicant’s claim for the benefit of a prior-filed TW113104082 filed on 02/02/2024 is acknowledged by the examiner.
Response to amendment/arguments
5. Applicant’s arguments with respect to the rejection of claims under 35 U.S.C. § 101 as the claimed invention is directed to a judicial exception (i.e., a law of nature, a natural phenomenon, or an abstract idea) without significantly more, have been fully considered. However, Examiner respectfully disagrees with the applicant’s argument. See response to arguments section. The rejection has been maintained.
6. Applicant’s arguments with respect to the rejection of claims under 35 U.S.C. § 102 (a)(i) and 103(a) have been fully considered but are moot in view of the new grounds of rejection. Please see the rejection as presented in this office action.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1 and 6 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claims 1 and 6 recite limitations “executing a survival path searching function according to the at least a survival value of the plurality of number sequences for a deep learning network”; “wherein the sorting circuit and the data distribution circuit are parallel processed to shorten a critical path; wherein the survival value is determined for the survival path searching function”. Even though the claim recital is mentioned verbatim in the specification, there is no description of what the survival value, survival path, how the survival value is calculated and also how the critical path is processed.
Response to 101 arguments
7. Applicants arguments on page 6 recites “The amended claim 1 specifies the feature "the sorting circuit and the data distribution circuit are parallel processed to shorten a critical path", which emphasizes that the numerical data processing method of the instant application reduces cascade circuits and achieves shorter critical path in the circuit design to perform data sorting and data distribution. More specifically, the instant application discloses that the encoding method determines a maximal value, a minimal value and at least a survival value of the plurality of number sequences according to a sorting result of the plurality of number sequences, and further performs a logic OR processing for an identical bit of each sequence of the plurality of number sequences to obtain a maximal value and a minimal value, and performs logic AND processing for the plurality of number sequences to determine a data value distribution of the plurality of original numerical values, which amounts to an improvement to another technology or technical field, meaning that claim element, or combination of claim elements, ensures claims 1-10 amount to significantly more than an abstract idea, and should be patentable under 35 U.S.C. 101”.
Examiner respectfully disagrees as the amended claim limitations recites “number sequences are one-hot encoding” is a data preprocessing technique that converts categorical, text-based, or integer-based data into a numerical format, that under broadest reasonable interpretation, covers performance of the limitation in the mind. Similarly “determining a maximal value, a minimal value and at least a survival value of the plurality of number sequences” under broadest reasonable interpretation, covers performance of the limitation in the mind. There is, nothing in the claim element that precludes the steps from practically being performed by a human mentally or with pen and paper. This limitations, at the high level of generality as drafted, would encompass a user to map categorical, text-based, or integer-based data into binary vectors by placing a 1 in the column representing its category and 0 in all others. Regarding dependent claims recite “performing a logic AND, OR processing for an identical bit of each sequence” that under broadest reasonable interpretation, covers performance of the limitation in the mind based logic AND, OR processing, but for generic computer components “processor”, “circuits”. There is, nothing in the claim element that precludes the steps from practically being performed by a human mentally or with pen and paper. If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the mind but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea.
Further the amended limitation the sorting and distribution working in parallel are common basic functions in computer technology using a programmed computer with logic and/or mathematical operation, are recited at a high level of generality and do not place meaningful limits on the abstract idea. These limitations are essentially steps data gathering steps which is an insignificant extra solution activity. There is nothing in the claim which precludes the steps from practically being performed in the human mind. Additionally, the mere nominal recitation of a generic computer components, or a programmed computer does not take the claim limitation out of the mental processes grouping. The combination of these additional elements are no more than mere instructions to apply the exception using series of steps. Accordingly, even in combination, the additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea.
This judicial exception is not integrated into a practical application. In particular, the claim recites the additional elements of, the invention being “Field Programmable Gate Array (FPGA),”, “processing device”, “shifter circuit”, “distribution circuit”, “adder circuit” are recited at a high level of generality as generic computer components that merely uses computers as a tool to perform the processes. These additional elements amount to nothing more than mere instructions to apply the recited abstract idea on a computer, under MPEP 2106.05(f). Combination of these additional elements is no more than mere instructions to apply the exception using series of steps and outputting the result of the mental process. Accordingly, even in combination, the additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea.
The claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the recitation of generic computing components is still mere instructions to apply the exception under MPEP 2106.05(f) and does not provide significantly more. Considering the additional elements in combination and the claim as a whole does not change the analysis, and does not amount to significantly more. Thus the claims are abstract.
Further, the specification and Claims does not provide any specific process with respect to the argued functions that would transform/ align/ arrange the data beyond what is well understood. Arrangement of the data such as sorting the data and distributing data in the context of this claim encompasses the user mentally sort and distribute the data. Examiner further notes that disclosing that the current invention is improvement without disclosing the inventive steps that are considered as improvement in both the claims and the specification do not overcome the 35 USC 101 abstract idea rejection. There is, nothing in the claim elements that precludes the steps from practically being performed by a human mentally or with pen and paper. Thus, when viewed as an ordered combination, the claim limitations does not amount to significantly more than the abstract idea of content filtering (Step 2B: Yes). The claim is patent ineligible.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
8. Claims 1-4 and 6-9 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception (i.e., a law of nature, a natural phenomenon, or an abstract idea) without significantly more. Determining whether claims are statutory under 35 U.S.C. 101 involves a two-step analysis. Step 1 requires a determination of whether the claims are directed to the statutory categories of invention. Step 2 requires a determination of whether the claims are directed to a judicial exception without significantly more. Step 2 is divided into two prongs, with the first prong having a part 1 and part 2. See MPEP 2106; See 2019 Revised Patent Subject Matter Eligibility Guidance (2019 PEG).
Pursuant to Step 1, claim 6 recites a data processing device which are directed to the statutory category of a machine.
Pursuant to Step 2A, part 1, claims are analyzed to determine whether they are directed to an abstract idea. Under the 2019 PEG, claims are deemed to be directed to an abstract idea if they fall within one of the enumerated categories of (a) mathematical concepts, (b) certain methods of organizing human activity, and (c) mental processes. Here, claims 1 and 6 are directed to an abstract idea categorized under mental processes. Courts consider a mental process if it “can be performed in the human mind, or by a human using a pen and paper.” MPEP 2016(a)(2)(III). Courts also consider a mental process as one that can be performed in the human mind and is merely using a computer as a tool to perform the concept. MPEP 2016(a)(2)(III)(C)(3). Claims 1 and 6 recite limitation transforming a numerical number and manipulating the data utilizing one-hot encoding process and executing the search function using a deep learning network/ model is recited at a high level of generality that merely used computers and algorithms as a tool to perform the processes. See MPEP 2106(a)(2)(III). For example, claim 1 recites limitations of “transforming …plurality of number sequences”, “determining…”, “executing…” are recited at a high level of generality and do not place meaningful limits on the abstract idea which is a task that can be performed by a human with the use of the computer as a tool. These limitations are essentially steps of generating and manipulating data at a high level of generality, which can be performed by a person using a computer as a tool.
Pursuant to Step 2A, part 2, claims are analyzed to determine whether the recited abstract idea is integrated into a practical application. In this case, as explained above, claims 1 and 6 merely recite a mental process. The limitations “transforming …plurality of number sequences”, “determining…”, executing….” are mental process. While claims 1 and 6 recite additional components in the form of “processing device”, these components are recited at a high level of generality, which do not add meaningful limits on the recited abstract idea to integrate it into a practical application by providing an improvement to the functioning of a computer or technology, implementing the abstract idea with a particular machine or manufacture that is integral to the claim, effecting a transformation or reduction of a particular article to a different state or thing, nor applying the abstract idea in some meaningful way beyond linking its use to computer technology. See 2019 PEG. The limitation “number sequences are one-hot encoding” is a data preprocessing technique that converts categorical, text-based, or integer-based data into a numerical format, that under broadest reasonable interpretation, covers performance of the limitation in the mind. Similarly “determining a maximal value, a minimal value and at least a survival value of the plurality of number sequences” under broadest reasonable interpretation, covers performance of the limitation in the mind. There is, nothing in the claim element that precludes the steps from practically being performed by a human mentally or with pen and paper. This limitations, at the high level of generality as drafted, would encompass a user to map categorical, text-based, or integer-based data into binary vectors by placing a 1 in the column representing its category and 0 in all others. The additional elements “Field Programmable Gate Array (FPGA),”, “processing device”, “shifter circuit”, “distribution circuit”, “adder circuit” are recited at a high level of generality as generic computer components that merely uses computers as a tool to perform the processes. These additional elements amount to nothing more than mere instructions to apply the recited abstract idea on a computer, under MPEP 2106.05(f). Combination of these additional elements is no more than mere instructions to apply the exception using series of steps and outputting the result of the mental process. Accordingly, even in combination, the additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea.
Pursuant to Step 2B, claims are analyzed to determine whether they recite significantly more than the abstract idea. In other words, it is determined whether the claims provide an inventive concept. In this case, claims 1 and 6 do not recite limitations that amount to significantly more than the abstract idea. The limitations are steps involving processes that can be practically performed by a human with the aid of pen and paper, or as explained above, using a computer as a tool to perform the concept. Accordingly, even in combination, the additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea.
Claims 2, 7 recites “performing a logic OR…” is a processes, that under broadest reasonable interpretation, covers performance of the limitation in the mind. There is, nothing in the claim element precludes the steps from practically being performed by a human mentally or with pen and paper and likewise do not provide "significantly more" than the abstract idea for similar reasons as the independent claim. These limitations, at the high level of generality as drafted, would encompass a user to perform a logic to identify identical bit sequence, which is mentally performable as an evaluation or judgement. If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the mind and/or using a pen and paper but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea.
Claims 3, 8 recites “performing a logic AND…” is a processes, that under broadest reasonable interpretation, covers performance of the limitation in the mind. There is, nothing in the claim element precludes the steps from practically being performed by a human mentally or with pen and paper and likewise do not provide "significantly more" than the abstract idea for similar reasons as the independent claim. These limitations, at the high level of generality as drafted, would encompass a user to perform a logic to identify identical bit sequence, which is mentally performable as an evaluation or judgement. If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the mind and/or using a pen and paper but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea.
Claims 4, 9 recites “transforming the plurality of original numerical values into the plurality of number sequences is implemented by a Field Programmable Gate Array (FPGA).” do not recite limitations that amount to significantly more than the abstract idea for similar reasons as the independent claim. The limitations are steps involving processes that can be practically performed by a human with the aid of pen and paper, or as explained above, using a computer as a tool to perform the concept. For example, transforming the plurality of original numerical values into the plurality of number sequences by a Field Programmable Gate Array (FPGA). Combination of these additional elements is no more than mere instructions to apply the exception using series of steps and outputting the result of the mental process. Accordingly, even in combination, the additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea.
Response to 103 arguments
9. Applicants arguments on page 6 recites “Goryavskiy fails to disclose the feature "determining a maximal value, a minimal value and at least a survival value of the plurality of number sequences according to a sorting result of the plurality of number sequences" as required by claim 1 of the instant application”
Examiner respectfully disagrees and maintains the rejection as Goryavskiy teaches, “determining a maximal value, a minimal value and at least a survival value of the plurality of number sequences according to a sorting result of the plurality of number sequences” (Paragraph [0730], [0731] discloses, maximum, minimum and survival values for each bucket or a sequence. Examiner interprets survival value as the identified values between the maximum and minimum values in plurality of buckets/ sequences) as required by claim 1 of the instant application.
Therefore the argued limitation is taught by Goryavskiy et al and the rejection is maintained.
Note: there is no description of survival value in the claim or instant specification.
Claim Rejections - 35 U.S.C. § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
10. Claim(s) 1-4, 6-9 are rejected under 35 U.S.C. 103 as being unpatentable over Goryavskiy; Yuly (US 20240143276 A1) and in further view of Highnam; Kate (US 20200267182 A1).
Regarding independent claim 1, Goryavskiy; Yuly (US 20240143276 A1) teaches, a numerical data processing method, comprising: transforming a plurality of original numerical values of data into a plurality of number sequences (Paragraph [0193] discloses, numerical value transformed into plurality of number sequences);
and determining a maximal value, a minimal value and at least a survival value of the plurality of number sequences according to a sorting result of the plurality of number sequences (Paragraph [0730], [0731] the minimum and/or maximum value of a record key can be computed (i.e., determining maximum and minimum values), which determines whether the record still falls into the current or target bucket (Examiner interprets determining survival value as determining if the record falls current or target bucket), or the value at which it will fall into the adjacent bucket (preceding or succeeding bucket). Subsequently, comparing the key of the actual analyzed record with this boundary value allows determining whether the record belongs to the desired (e.g., current or target) bucket or confirms that it lies below (above) the next or previous bucket (which, in given specific implementation, may indirectly indicates whether the record belongs to the current or target bucket).
executing a survival path searching function according to the at least a survival value of the plurality of number sequences for a deep learning network; wherein the survival value is determined for the survival path searching function. (Paragraph [0117] discloses, executing searching strategy selection using machine learning models, classifiers, and neural networks, such as perceptrons, to determine parameters or select action strategies during the sorting or searching process, Paragraphs [0197], [0198] discloses, portion of the information contained in the record is utilized to derive or calculate a number (or a similar object) or a sequence thereof. It can also be interpreted as a string or used to obtain a string or a sequence of characters. Or it can be interpreted or used to derive a sequence consisting of multiple such objects.(Based on specifications Paragraph [0028] the sorting circuit 204 in FIG. 3 may determine required number or value the original numerical values, i.e., the survival values, to execute a survival path searching function for a deep learning network. Therefore the prior art discloses, executing the survival path in the specified range/ interval based on the searching strategy according to the plurality of the sequences using machine learning models));
Goryavskiy et al fails to explicitly teach, wherein the plurality of number sequences are one-hot encoding; wherein the sorting circuit and the data distribution circuit are parallel processed to shorten a critical path.
Highnam; Kate (US 20200267182 A1) teaches, wherein the plurality of number sequences are one-hot encoding (Fig. 4 Paragraph [0069] At step 506, each numeric value is transformed into a one-hot encoding vector. That is, a sequence of one-hot encoding vectors is generated to be used in later steps of process 500).
Therefore it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention, to have modified the teachings of Goryavskiy et al by providing wherein the plurality of number sequences are one-hot encoding, as taught by Highnam et al (Paragraph [0069]).
One of the ordinary skill in the art would have been motivated to make this modification, by doing so, One-hot encoding's main advantage is making categorical data usable by most machine learning algorithms by converting it into a numerical format that doesn't imply an order, which helps prevent biased results and improve model performance).
Goryavskiy et al and Highnam et al fails to explicitly teach, wherein the sorting circuit and the data distribution circuit are parallel processed to shorten a critical path.
Buchert, Ryan Samuel (US 20030123418 A1) teaches, wherein the sorting circuit and the data distribution circuit are parallel processed to shorten a critical path (claims 6, 9, 10 and 11 discloses, the sorter elements in the sorter circuit and the distributions circuit/ adder circuit operate in parallel (based on specification data distribution circuit 206 includes an adder circuit. Therefore examiner interprets data distribution circuit as adder circuit).
Note: the limitation “shorten a critical path” is an intended use and it does not specify how the critical path is shortened”
Therefore it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention, to have modified the teachings of Goryavskiy et al and Highnam et al by providing wherein the sorting circuit and the data distribution circuit are parallel processed to shorten a critical path, as taught by Buchert et al (claims 6, 9, 10 and 11).
One of the ordinary skill in the art would have been motivated to make this modification, by doing so, processing the set of channel responses with parallel inputs to each sorter element minimizes the operating time of the system such that the number of clock cycles is equal to the number of channel response values processed).
Regarding dependent claim 2, Goryavskiy et al, Highnam et al and Buchert et al teach, the numerical data processing method of claim 1.
Goryavskiy et al further teaches, wherein the step of determining the maximal value, the minimal value and the at least a survival value of the plurality of number sequences according to the sorting result of the plurality of number sequences comprises: performing a logic OR processing for an identical bit of each sequence of the plurality of number sequences to obtain a first sequence (Paragraph [0110] discloses, performing a logic OR obtaining a number sequence for a fixed length of the digit or symbol for each sequence);
and taking a corresponding value of a leading value 1 of the first sequence as a maximal value of the plurality of original numerical values, and taking a corresponding value of a last value 1 of the first sequence as a minimal value of the plurality of original numerical values (Paragraph [0731] discloses, the minimum and maximum key values in the record in a bin/ bucket/ sequence. Also see [0016]).
Regarding dependent claim 3, Goryavskiy et al, Highnam et al and Buchert et al teach, the numerical data processing method of claim 1.
Goryavskiy et al further teaches, wherein the step of determining the maximal value, the minimal value and the at least a survival value of the plurality of number sequences according to the sorting result of the plurality of number sequences comprises: performing a logic AND processing for an identical bit of each sequence of the plurality of number sequences to obtain a second sequence (Paragraph [0718] discloses, performing a logic AND by excluding the common or insignificant parts of the keys);
and determining a data value distribution of the plurality of original numerical values according to the second sequence (Paragraph [0719] discloses distribution of the original key values according to the second sequence/ modified values).
Regarding dependent claim 4, Goryavskiy et al, Highnam et al and Buchert et al teach, the numerical data processing method of claim 1.
Goryavskiy et al further teaches, wherein transforming the plurality of original numerical values into the plurality of number sequences is implemented by a Field Programmable Gate Array (FPGA) (Paragraph [0163] discloses, simulated specialized ASIC or programmable logic array (PLA, FPGA) are used in data processing, which can be transforming the plurality of original numerical values into the plurality of number sequences).
Regarding independent claim 6, Goryavskiy; Yuly (US 20240143276 A1) teaches, a numerical data processing device, comprising: a shifter circuit, for receiving a plurality of original numerical values of data and transforming the plurality of original numerical values of the data into a plurality of number sequences (Paragraph [0193] discloses, numerical value transformed into plurality of number sequences);
a sorting circuit, for sorting the plurality of number sequences and determining a maximal value, a minimal value of the plurality of number sequences according to a sorting result of the plurality of number sequences (Paragraph [0730], [0731] the minimum and/or maximum value of a record key can be computed (i.e., determining maximum and minimum values), which determines whether the record still falls into the current or target bucket (Examiner interprets determining survival value as determining if the record falls current or target bucket), or the value at which it will fall into the adjacent bucket (preceding or succeeding bucket). Subsequently, comparing the key of the actual analyzed record with this boundary value allows determining whether the record belongs to the desired (e.g., current or target) bucket or confirms that it lies below (above) the next or previous bucket (which, in given specific implementation, may indirectly indicates whether the record belongs to the current or target bucket).
and a data distribution circuit, for determining at least a survival value according to the plurality of number sequences (Paragraph [0808] discloses, executing the survival path/ optimal path in sorting process according to plurality of bins/ buckets/ sequence number utilizing machine learning process (Examiner interprets survival path as optimal path));
wherein the survival value is determined for a survival path searching function; wherein the data distribution circuit further includes a value distribution/classification circuit for executing the survival path searching function according to the at least a survival value of the plurality of number sequences for a deep learning network; wherein the survival value is determined for a survival path searching function (Paragraph [0117] discloses, executing searching strategy selection using machine learning models, classifiers, and neural networks, such as perceptrons, to determine parameters or select action strategies during the sorting or searching process, Paragraphs [0197], [0198] discloses, portion of the information contained in the record is utilized to derive or calculate a number (or a similar object) or a sequence thereof. It can also be interpreted as a string or used to obtain a string or a sequence of characters. Or it can be interpreted or used to derive a sequence consisting of multiple such objects.(Based on specifications Paragraph [0028] the sorting circuit 204 in FIG. 3 may determine required number or value the original numerical values, i.e., the survival values, to execute a survival path searching function for a deep learning network. Therefore the prior art discloses, executing the survival path in the specified range/ interval based on the searching strategy according to the plurality of the sequences using machine learning models));
Goryavskiy et al fails to explicitly teach, wherein the plurality of number sequences are one-hot encodings wherein the sorting circuit and the data distribution circuit are parallel processed to shorten a critical path;
Highnam; Kate (US 20200267182 A1) teaches, wherein the plurality of number sequences are one-hot encoding (Fig. 4 Paragraph [0069] At step 506, each numeric value is transformed into a one-hot encoding vector. That is, a sequence of one-hot encoding vectors is generated to be used in later steps of process 500).
Therefore it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention, to have modified the teachings of Goryavskiy et al by providing wherein the plurality of number sequences are one-hot encoding, as taught by Highnam et al (Paragraph [0069])..
One of the ordinary skill in the art would have been motivated to make this modification, by doing so, One-hot encoding's main advantage is making categorical data usable by most machine learning algorithms by converting it into a numerical format that doesn't imply an order, which helps prevent biased results and improve model performance).
Goryavskiy et al and Highnam et al fails to explicitly teach, wherein the sorting circuit and the data distribution circuit are parallel processed to shorten a critical path.
Buchert, Ryan Samuel (US 20030123418 A1) teaches, wherein the sorting circuit and the data distribution circuit are parallel processed to shorten a critical path (claims 6, 9, 10 and 11 discloses, the sorter elements in the sorter circuit and the distributions circuit/ adder circuit operate in parallel (based on specification data distribution circuit 206 includes an adder circuit. Therefore examiner interprets data distribution circuit as adder circuit).
Note: the limitation “shorten a critical path” is an intended use and it does not specify how the critical path is shortened”
Therefore it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention, to have modified the teachings of Goryavskiy et al and Highnam et al by providing wherein the sorting circuit and the data distribution circuit are parallel processed to shorten a critical path, as taught by Buchert et al (claims 6, 9, 10 and 11).
One of the ordinary skill in the art would have been motivated to make this modification, by doing so, processing the set of channel responses with parallel inputs to each sorter element minimizes the operating time of the system such that the number of clock cycles is equal to the number of channel response values processed).
Regarding dependent claim 7, Goryavskiy et al, Highnam et al and Buchert et al teach, the numerical data processing device of claim 6.
Goryavskiy et al further teaches, wherein the sorting circuit includes a logic OR circuit and a leading/last 1 detecting circuit, for performing a logic OR processing for an identical bit of each sequence of the plurality of number sequences to obtain a first sequence (Paragraph [0110] discloses, performing a logic OR obtaining a number sequence for a fixed length of the digit or symbol for each sequence);
and for taking, by the leading/last 1 detecting circuit, a corresponding value of a leading value 1 of the first sequence as a maximal value of the plurality of original numerical values, and taking a corresponding value of a last value 1 of the first sequence as a minimal value of the plurality of original numerical values(Paragraph [0731] discloses, the minimum and maximum key values in the record in a bin/ bucket/ sequence. Also see [0016]).
Regarding dependent claim 8, Goryavskiy et al, Highnam et al and Buchert et al teach, the numerical data processing device of claim 6.
Goryavskiy et al further teaches, wherein the data distribution circuit includes an adder circuit and a value distribution/classification circuit, for performing a logic AND processing for an identical bit of each sequence of the plurality of number sequences to obtain a second sequence (Paragraph [0718] discloses, performing a logic AND by excluding the common or insignificant parts of the keys);
and determining, by the value distribution/classification circuit, a data value distribution of the plurality of original numerical values according to the second sequence (Paragraph [0719] discloses distribution of the original key values according to the second sequence/ modified values).
Regarding dependent claim 9, Goryavskiy et al, Highnam et al and Buchert et al teach, the numerical data processing device of claim 6.
Goryavskiy et al further teaches, wherein transforming the plurality of original numerical values into the plurality of number sequences is implemented by a Field Programmable Gate Array (FPGA) (Paragraph [0163] discloses, simulated specialized ASIC or programmable logic array (PLA, FPGA) are used in data processing, which can be transforming the plurality of original numerical values into the plurality of number sequences).
Closest Prior Art
11. The prior art made of record and not relied upon is considered pertinent to the applicant’s disclosure.
MUKUGE; Masakazu (US 20220078287 A1) teaches, A signaling gateway apparatus (SG) in an IP network, is directly connected to a group unit center (GC) in a PSTN in a layer of MTP level 3 without via a signaling transfer point (STP), converts a M2PA sequence number included in an XCO or an XCA which is a response to the XCO, to a sequence number with a value in a range from 0 to 127 which is a maximum value of a 7-bit unsigned integer and transmits the XCO or the XCA to an opposite apparatus (Abstract).
12. Examiner has pointed out particular references contained in the prior arts of record in the body of this action for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and Figures may apply as well. It is respectfully requested from the applicant, in preparing the response, to consider fully the entire references as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior arts or disclosed by the examiner. It is noted that any citation to specific pages, columns, figures, or lines in the prior art references any interpretation of the references should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. In re Heck, 699 F.2d 1331-33, 216 USPQ 1038-39 (Fed. Cir. 1983) (quoting In re Lemelson, 397 F.2d 1006, 1009, 158 USPQ 275, 277 (CCPA 1968))).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUMAN RAJAPUTRA whose telephone number is (571) 272-4669. The examiner can normally be reached between 8:00 AM - 5:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tony Mahmoudi (571) 272-4078 can be reached. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/ patents/ apply/ patent-center for more information about Patent Center and https://www.uspto.gov/ patents/ docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/S. R./
Examiner, Art Unit 2163
/TONY MAHMOUDI/Supervisory Patent Examiner, Art Unit 2163
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