DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Semiconductor Device that Includes an Insulating Layer with a Groove.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 8, 10-11, and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kumazawa et al (US 2018/0286974).
Regarding Claim 1, Kumazawa et al discloses a semiconductor device (MOSFET 10 [0058] Fig 1 and Fig 16), comprising:
a semiconductor layer (p-type region 26B, drift region 28, and drain region 30 [0042]-[0045] Fig 16);
a first wiring line (contact region 26a n+, p+, n+ (left) [0042] shown in annotated Fig 16) and a second wiring line (contact region 26a n+, p+, n+ (right) [0042] shown in annotated Fig 16) that are formed on the semiconductor layer (26b, 28, 30 Fig 16) and spaced apart from each other;
an insulating layer (interlayer insulating film 50 [0039] Fig 16) that covers the first wiring line (26a n+, p+, n+ (left) shown in annotated Fig 16), the second wiring line (26a n+, p+, n+ (right) shown in annotated Fig 16), and an inter-wiring line region (contact layers 80a [0039] Fig 16) between the first wiring line (26a n+, p+, n+ (left) shown in annotated Fig 16) and the second wiring line (26a n+, p+, n+ (right) shown in annotated Fig 16), and includes a first opening (shown in annotated Fig 16) that exposes a part of the first wiring line (26a n+, p+, n+ (left) shown in annotated Fig 16) and a second opening (shown in annotated Fig 16) that exposes a part of the second wiring line (26a n+, p+, n+ (right) shown in annotated Fig 16);
a first electrode (intermediate layer 82b comprising aluminum silicide [0039] shown in annotated Fig 16) that is formed to extend over the first wiring line (26a n+, p+, n+ (left) shown in annotated Fig 16) and the insulating layer (50 Fig 16), the first wiring line (26a n+, p+, n+ (left) shown in annotated Fig 16) being exposed through the first opening (shown in annotated Fig 16), the first electrode (82b shown in annotated Fig 16) including a first edge (shown in annotated Fig 16) located on the insulating layer (50 Fig 16); and
a second electrode (intermediate layer 82b comprising aluminum silicide [0039] shown in annotated Fig 16) that is formed to extend over the second wiring line (26a n+, p+, n+ (right) shown in annotated Fig 16) and the insulating layer (50 Fig 16), the second wiring line (26a n+, p+, n+ (right) shown in annotated Fig 16) being exposed through the second opening (shown in annotated Fig 16), the second electrode (82b shown in annotated Fig 16) including a second edge (shown in annotated Fig 16) located on the insulating layer (50 Fig 16),
wherein the insulating layer (50 Fig 16) includes an interposed portion (shown in annotated Fig 16) interposed between the first edge (shown in annotated Fig 16) and the second edge (shown in annotated Fig 16) that are opposed to each other,
the interposed portion (shown in annotated Fig 16) includes a groove (shown in annotated Fig 16) that is recessed toward the semiconductor layer (26b, 28, 30 Fig 16) from an upper surface of the interposed portion (shown in annotated Fig 16), and
the groove (shown in annotated Fig 16) extends along at least one of the first edge (shown in annotated Fig 16) and the second edge (shown in annotated Fig 16).
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Regarding Claim 2, Kumazawa et al discloses the limitations of claim 1 as explained above. Kumazawa et al further discloses
wherein the groove (shown above in annotated Fig 16) extends over the entire interposed portion (shown above in annotated Fig 16).
Regarding Claim 3, Kumazawa et al discloses the limitations of claim 1 as explained above. Kumazawa et al further discloses
wherein the interposed portion (shown above in annotated Fig 16) covers (covers in the horizontal x direction Fig 16) the inter-wiring line region (80a Fig 16), and the groove (shown above in annotated Fig 16) is formed at a position different from the inter-wiring line region (80a Fig 16) as viewed from a thickness direction (vertical y direction Fig 16) of the semiconductor layer (26b, 28, 30 Fig 16).
Regarding Claim 8, Kumazawa et al discloses the limitation of claim 1 as explained above. Kumazawa et al further discloses further comprising:
a third wiring line (contact region 26a n+, p+, n+ (middle left) [0042] shown in annotated Fig 16) that is formed on the semiconductor layer (26b, 28, 30 Fig 16) and spaced apart from both the first wiring line (26a n+, p+, n+ (left) shown in annotated Fig 16) and the second wiring line (26a n+, p+, n+ (right) shown in annotated Fig 16); and
a third electrode (82b shown in annotated Fig 16) spaced apart from both the first electrode (82b shown in annotated Fig 16) and the second electrode (82b shown in annotated Fig 16),
wherein the insulating layer (50 Fig 16) further covers the third wiring line (82b shown in annotated Fig 16),
a second inter-wiring line region (contact layers 80a [0039] Fig 16) between the first wiring line and the third wiring line (26a n+, p+, n+ (middle left) shown in annotated Fig 16), and a third inter-wiring line region (contact layers 80a [0039] Fig 16) between the second wiring line (26a n+, p+, n+ (right) shown in annotated Fig 16) and the third wiring line (26a n+, p+, n+ (middle left) shown in annotated Fig 16), and
includes a third opening (shown in annotated Fig 16) that exposes a part of the third wiring line (26a n+, p+, n+ (middle left) shown in annotated Fig 16), the third electrode (82b shown in annotated Fig 16) is formed to extend over the third wiring line (26a n+, p+, n+ (middle left) shown in annotated Fig 16) and the insulating layer (50 Fig 16), the third wiring line (26a n+, p+, n+ (middle left) shown in annotated Fig 16) being exposed through the third opening (shown in annotated Fig 16), the third electrode (82b shown in annotated Fig 16) including a third edge (shown in annotated Fig 16) located on the insulating layer (50 Fig 16),
a second interposed portion (shown in annotated Fig 16), interposed between the first edge (shown in annotated Fig 16) and the third edge (shown in annotated Fig 16) that are opposed to each other, includes a second groove (shown in annotated Fig 16) recessed toward the semiconductor layer (26b, 28, 30 Fig 16) from an upper surface of the second interposed portion (shown in annotated Fig 16),
a third interposed portion (shown in annotated Fig 16), interposed between the second edge (shown in annotated Fig 16) and the third edge (shown in annotated Fig 16) that are opposed to each other, includes a third groove (shown in annotated Fig 16) recessed toward the semiconductor layer (26b, 28, 30 Fig 16) from an upper surface of the third interposed portion (shown in annotated Fig 16),
the second groove (shown in annotated Fig 16) extends along at least one of the first edge (shown in annotated Fig 16) and the third edge (shown in annotated Fig 16), and the third groove (shown in annotated Fig 16) extends along at least one of the second edge (shown in annotated Fig 16) and the third edge (shown in annotated Fig 16).
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Regarding Claim 10, Kumazawa et al discloses the limitations of claim 1 as explained above. Kumazawa et al further discloses
wherein the first electrode (80b shown in annotated Fig 16) includes:
a section (shown in annotated Fig 16) formed on the first wiring line (26a n+, p+, n+ (left) shown in annotated Fig 16);
a section (shown in annotated Fig 16) formed on an upper surface of the insulating layer (50 Fig 16); and
a first connection section (shown in annotated Fig 16) that is formed on a first side surface defining the first opening (shown in annotated Fig 16), and that connects the section (shown in annotated Fig 16) formed on the first wiring line (26a n+, p+, n+ (left) shown in annotated Fig 16) and the section (shown in annotated Fig 16) formed on the upper surface of the insulating layer (50 Fig 16), and
the second electrode (80b shown in annotated Fig 16) includes: a section (shown in annotated Fig 16) formed on the second wiring line (26a n+, p+, n+ (right) shown in annotated Fig 16);
a section (shown in annotated Fig 16) formed on an upper surface of the insulating layer (50 Fig 16); and
a second connection section (shown in annotated Fig 16) that is formed on a second side surface defining the second opening (shown in annotated Fig 16), and that connects the section (shown in annotated Fig 16) formed on the second wiring line and the section (shown in annotated Fig 16) formed on the upper surface of the insulating layer (50 Fig 16).
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Regarding Claim 11, Kumazawa et al discloses the limitations of claim 1 as explained above. Kumazawa et al further discloses
wherein the insulating layer (50 Fig 16) includes:
a first insulating film (first insulating layer 51 [0038] Fig 16) formed on the first wiring line (26a n+, p+, n+ (left) shown above in annotated Fig 16) and the second wiring line (26a n+, p+, n+ (right) shown above in annotated Fig 16); and
a second insulating film (second insulating layer 52 [0038] Fig 16) formed on the first insulating film (51 Fig 16), and the groove (shown above in annotated Fig 16) extends through the second insulating film (52 Fig 16).
Regarding Claim 15, Kumazawa et al discloses the limitations of claim 11 as explained above. Kumazawa et al further discloses
wherein the second insulating film (52 Fig 16) is thicker (shown in Fig 16) than the first insulating film (51 Fig 16).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Kumazawa et al (US 2018/0286974) in view of Kawana et al (US 2018/0250751).
Regarding Claim 9, Kumazawa et al discloses the limitations of claim 1 as explained above. Kumazawa et al does not disclose
wherein at least one of the first electrode and the second electrode is made of a material including Ag.
Xue et al, in the related art of semiconductor devices that include MOSFETs, discloses
wherein at least one of the first electrode (first electrode 22 [0117] Fig 5) and the second electrode (second electrode 24 [0117] Fig 5) is made of a material including Ag (silver [0117]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Kumazawa et al to include wherein at least one of the first electrode and the second electrode is made of a material including Ag as taught by Kawana et al in order to improve heat dissipation [0119] and improve electrical function capability. Further, a person of ordinary skill in the art would have recognized that having at least one of the electrodes made of silver would be a simple substitution of one known element for another to obtain predictable results (see MPEP 2143.I(B) (suitable alternate)).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Kumazawa et al (US 2018/0286974) in view of Katsuyoshi et al (JP 4050004).
Regarding Claim 12, Kumazawa et al discloses the limitations of claim 11 as explained above. Kumazawa et al does not directly disclose
wherein the first insulating film has a lower moisture content than the second insulating film.
Katsuyoshi et al, in the related art of semiconductor devices that include MOSFETs, discloses
wherein the first insulating film (first insulating film [0013]) has a lower moisture content (reduced moisture content [0013]) than the second insulating film (second insulating film [0013]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Kumazawa et al to include wherein the first insulating film has a lower moisture content than the second insulating film as taught by Katsuyoshi et al in order to optimize the crystal orientation to improve adhesion which would reduce the possibility of pealing [0008]-[0012]. Further, a person of ordinary skill in the art would have recognized that optimizing the crystal orientation and improving adhesion would improve the durability and reliability of the device (see MPEP 2143.I(D)).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Kumazawa et al (US 2018/0286974) in view of Kim et al (US 2021/0288005).
Regarding Claim 14, Kumazawa et al discloses the limitations of claim 11 as explained above. Kumazawa et al does not disclose
wherein the first insulating film is made of a material including silicon nitride, and the second insulating film is made of a material including polyimide.
Kim et al, in the related art of semiconductor devices that include MOSFETs, discloses
wherein the first insulating film (first insulating layer 131 [0054] Fig 2) is made of a material including silicon nitride (silicon nitride [0054]), and the second insulating film (second insulating layer 132 [0054] Fig 2) is made of a material including polyimide (polyimide [0054]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Kumazawa et al to include wherein the first insulating film is made of a material including silicon nitride, and the second insulating film is made of a material including polyimide as taught by Kim et al in order to protect the device and prevent unnecessary electrical short circuits [0050]. Further, a person of ordinary skill in the art would have recognized that having a first insulating film made of silicon nitride and a second insulating film made of polyimide would be a simple substitution of one known element for another to obtain predictable results (see MPEP 2143.I(B) (suitable alternate)).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Kumazawa et al (US 2018/0286974) in view of Kwon et al (US 2021/0343656).
Regarding Claim 16, Kumazawa et al discloses the limitations of claim 11 as explained above.
Kumazawa et al further discloses
a cross-sectional structure of the groove (shown above in annotated Fig 16) in a direction perpendicular to a direction wherein the groove (shown above in annotated Fig 16) extends has a curved shape (shown in Fig 16) recessed toward an inside of the second insulating film (52 Fig 16) with respect to an end portion at a lower surface of the second insulating film (52 Fig 16).
Kumazawa et al does not disclose
wherein the second insulating film is made of a material including non-photosensitive polyimide.
Kwon et al, in the related art of semiconductor devices that include MOSEFTs, discloses
wherein the second insulating film (second insulating layer 133a [0042] Fig 2) is made of a material including non-photosensitive polyimide (non-photosensitive polyimide [0042]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Kumazawa et al to include wherein the second insulating film is made of non-photosensitive polyimide as taught by Kwon et al in order to enhance adhesion between the layers [005]-[0006]. Further, a person of ordinary skill in the art would have recognized that improving adhesion between the layers of the device would be advantageous in optimizing the reliability and durability of the device (see MPEP 2143.I(D)). Additionally, a person of ordinary skill in the art would have recognized that having the second insulating film made of non-photosensitive polyimide would be a simple substitution of one known element for another to obtain predictable results (see MPEP 2143.I(B) (suitable alternate)).
Allowable Subject Matter
Claims 4-7 and 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 4:
Regarding Claim 4, Kumazawa et al (US 2018/0286974) discloses the limitations of claim 1 as explained above.
The reason for the indication of allowability of Claim 4 is the inclusion of
wherein, as viewed from a thickness direction of the semiconductor layer, the groove has a greater width than the inter-wiring line region.
Specifically, Fig 16 of Kumazawa et al does not disclose a plan view wherein the thickness direction of the semiconductor layer, the groove has a width greater or smaller than that of the inter-wiring line region. Further, should another reference be found that discloses this feature, it would not be obvious to a person of ordinary skill in the art to combine the references to include this feature.
It is these features found in the claim, as they are claimed in the combination that has not been found, taught or suggested by the prior art of record, which makes this claim allowable over the prior art.
Claim 5:
Regarding Claim 5, Kumazawa et al (US 2018/0286974) discloses the limitations of claim 1 as explained above. Kumazawa et al (US 2018/0286974) further discloses
wherein the semiconductor device (MOSFET 10 [0058] Fig 1 and Fig 16) includes a MOSFET, and the first electrode (80b Fig 16) is a source electrode (source electrode 80 [0033] Fig 16).
The reason for the indication of allowability of Claim 5 is the inclusion of
the second electrode is a gate electrode.
Specifically, the prior art reference Kumazawa discloses the gate electrode (gate electrode 40 [0034] Fig 16) directly below the first insulating layer (50 Fig 16) and would not meet claim limitations of Claim 1 (from which Claim 5 depends) if interpreted in a way that is different from the above interpretation that was applied. Further, should another reference be found that discloses this claim interpretation, it would not be obvious to a person of ordinary skill in the art to combine the references to include this feature.
It is these features found in the claim, as they are claimed in the combination that has not been found, taught or suggested by the prior art of record, which makes this claim allowable over the prior art.
Claims 6-7 would be allowable based on their dependency on Claim 5.
Claim 13:
Regarding Claim 13, the combination of Kumazawa et al (US 2018/0286974) and Katsuyoshi et al (JP 4050004) discloses the limitations of claim 12 as explained above.
The reason for the indication of allowability of Claim 13 is the inclusion of
further comprising: a sealing plastic covering the first electrode, the second electrode, and the insulating layer, wherein the groove is filled with the sealing plastic, and the sealing plastic has a lower moisture content than the second insulating film.
Specifically, the prior art reference Kumazawa et al does not disclose a sealing plastic covering the electrodes 80 in Fig 16. Although a prior art reference may be found that includes a sealing plastic which may be found to be obvious to combine with Kumazawa et al, when combined, there would be no way for the grooves of the insulating layer to be sealed with the plastic because the electrodes 80 would be over the top of the grooves and would prevent the plastic from entering the groove. A secondary reference may be found that discloses the sealing plastic between the insulating layer and the electrode in the vertical direction which may be possible to combine with Kumazawa et al, however, no such reference has yet been found.
It is these features found in the claim, as they are claimed in the combination that has not been found, taught or suggested by the prior art of record, which makes this claim allowable over the prior art.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Related Cited Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Suganuma (US 2020/0381421) which discloses a MOSFET having an active layer [0003], and Ryan et al (US 2015/0126028) which discloses MOSFETs with a gate electrode as a control electrode [0002].
Conclusion
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/D.P.S./Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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