Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This application has been examined. Claims 1-13 are pending.
The Group and/or Art Unit location of your application in the PTO has changed. To aid in correlating any papers for this application, all further correspondence regarding this application should be directed to Group Art Unit 2175.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 3 are rejected under 35 U.S.C. § 102(a)(2) as being anticipated by Reis et al. (US Pub No. 2002/0049558).
In regard to claim 1, Reis et al. disclose a semiconductor device comprising: a first semiconductor circuit (item 700 of figure 7) having a counter circuit (item 702 of figure ) configured to count in synchronization with a first clock signal and generate a readout signal when the count reaches a predetermined number (as shown in Fig. 7, which is reproduced below for ease of reference and convenience, Reis discloses the delay circuit 700 including a virtual circuit comprising n boundary scan cells is in practice a counter 702, the value of which is increased in synchronization with the clock signal of the JTAG controller in the test equipment. The state machine 706 obtains the amount of incoming data from the counter 708 and observes the value of the counter 702. When the value obtains the determined value n, the state machine 706 controls the buffer to release the buffered TDO data to the test access port TAP See ¶ 37);
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a buffer (item 704 of figure 7) configured to store test data and sequentially output the test data in the order stored in synchronization with the first clock signal when the readout signal indicates a valid value (in Reis, the counter being provided with a threshold value responsive to said delay, and when the threshold value is exceeded the buffer is configured to release the buffered test data output to said interface. See ¶ 37 and claim 11); and a first scan test circuit configured to sequentially capture the test data output from the buffer in synchronization with the first clock signal (in Reis, when the value obtains the determined value n, the state machine 706 controls the buffer to release the buffered TDO data to the test access port TAP. See ¶ 37).
In regard to claim 3, Reis et al. disclose a setting register capable of setting any value from outside the semiconductor device for the predetermined number, the semiconductor device (in Reis, the delays that must be considered when determining the value of variable n include delays created in the encoding and decoding required by the higher data transmission protocols, transmission path delays and TAP interface synchronization delay of the TDO signal. In addition, such situations may occur during testing, where test data must be buffered also in the device under test, which should also be taken into account as a delay. See ¶ 36).
Examiner's note:
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the Applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the Applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passages as taught by the prior art or disclosed by the Examiner.
Allowable Subject Matter
Claims 10-13 are allowable over the prior of records.
Claims 2, 4-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an Examiner's statement of reasons for the indication of allowable subject matter: Claims 2, 5, 10, 12 are allowable over the prior art of record because the prior arts, cited in its entirety, or in combination, do not teach
wherein the counter circuit includes: a counter register that counts up, counts down, or makes a regular change similar to these in synchronization with the first clock signal; and a comparator that determines the match and mismatch between the value of the counter register and the predetermined number, wherein the semiconductor device is configured to perform a count operation when the scan enable is valid and the comparator indicates a mismatch, and is configured to enable the readout signal when the scan enable is valid and the comparator indicates a match, the semiconductor device (claim 2);
a second semiconductor circuit, wherein the first semiconductor circuit further includes an input terminal and a receiving circuit that sequentially writes the test data input to the input terminal into the buffer in synchronization with a second clock signal, and wherein the second semiconductor circuit includes a second scan test circuit that captures test data input from outside in synchronization with a third clock signal, an output terminal, and a transmission circuit that outputs the test data output by the second scan test circuit to the output terminal in synchronization with a fourth clock signal, and wherein the input terminal is connected to the output terminal (claim 5);
a semiconductor diagnostic device that diagnoses a first semiconductor circuit, comprising: a transmission circuit that outputs the test data output by the first scan test circuit to the output terminal in synchronization with the second clock signal; a first test device; and a second test device comprising: an output terminal connected to the input terminal of the first semiconductor circuit; a transmission circuit that outputs the test data input from the first test device in synchronization with a third clock signal to the output terminal in synchronization with a fourth clock signal; a counter circuit configured to count in synchronization with the third clock signal and generate a readout signal when the count reaches a predetermined number; a buffer configured to store test data and sequentially output the test data in synchronization with the third clock signal when the readout signal indicates a valid value; an input terminal connected to the output terminal of the first semiconductor circuit; a reception circuit that sequentially writes the test data input to the input terminal into the buffer in synchronization with the fourth clock signal; and an output terminal from which the test data from the buffer is output (claim 10);
a semiconductor device comprising a second semiconductor circuit includes: an output terminal connected to the input terminal of the first semiconductor circuit, a transmission circuit that outputs test data input from a debug device in synchronization with a third clock signal to the output terminal in synchronization with a fourth clock signal, a counter circuit configured to count in synchronization with the third clock signal and generate a readout signal when the count reaches a predetermined number, a buffer configured to store test data and sequentially output the test data in the order stored in synchronization with the third clock signal when the readout signal indicates a valid value, an input terminal connected to the output terminal of the first semiconductor circuit, a reception circuit that sequentially writes the test data input to the input terminal into the buffer in synchronization with the fourth clock signal, and an output terminal from which the test data from the buffer is output (claim 12).
Conclusion
Claims 1 and 3 are rejected. Claims 2, 4-9 are objected. Claims 10-13 are allowed.
The prior arts made of record and not relied upon are considered pertinent to applicant's disclosure.
Tsukuda et al., US Pub No. 2022/0163584, teach a transmitting-side hierarchical block includes a first logic circuit and an output control circuit connected to the first logic circuit and controlling an output signal of the transmitting-side hierarchical block. The receiving-side hierarchical block includes a second logic circuit being scan test target and operating by receiving the output signal of the transmitting-side hierarchical block, and a test control circuit controlling the scan test of the second logic circuit.
Shin et al., US Pub No. 2020/0225284, teach an inverting circuit on a feedback path of the first scan register; a second scan register in the first core; and a logic circuit on a data path between the first scan register and the second scan register. In a test mode for an AT-SPEED test of the logic circuit, the inverting circuit generates test data by inverting scan data that are output from the first scan register, the first scan register stores the test data in response to a first pulse of a clock signal, the logic circuit generates result data based on the test data that are output from the first scan register, and the second scan register stores the result data in response to a second pulse of the clock signal.
Meada et al., US Pub No. 2018/0059183, teach a FIFO, a test data write circuit that sequentially writes a plurality of test data to the FIFO in synchronization with a first clock signal, and a test control circuit that, in parallel with writing of the plurality of test data to the FIFO by the test data write circuit, sequentially reads a plurality of test data stored in the FIFO in synchronization with a second clock signal that is not synchronous with the first clock signal and performs a scan test of a circuit to be tested. (Abstract,
Okada et al., US Pub No. 2006/0041806, teach a semiconductor device including a plurality of first scan chains configured such that the register circuits in the test object circuit are serially connected, and a plurality of second scan chains configured such that the register circuits in the non-test object circuit are serially connected, the testing method including: providing test data to the first and second scan chains, and inputting the clock signal to the first scan chains, not inputting the clock signal to the second scan chains.
Kobayashi, US Pub No. 2003/0056183, teaches the number of scan chains within the chip of an LSI to be tested is n, the number of scan inputs given from the outside of the LSI is m, and the number of scan outputs output to the outside of the LSI is p, this scan test circuit is equipped with a scan input conversion circuit which carries out bit number conversion m-n, and a scan output conversion circuit which carries out bit number conversion of n-p..
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/RAYMOND N PHAN/
Primary Examiner, Art Unit 2175