DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1, 12 and 17 recite “a plurality of taps”. It is unclear to the Examiner what constitute a “tap” in the context of the claim and structure applicant refer.
Claims 2-11, 13-16 and 18-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being depended on claims 1, 12 and 17.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 12 and 16 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Malloug et al. Mostly-digital design of sinusoidal signal generators for mixed-signal BIST applications using harmonic cancellation (NPL cited by Applicants).
Regarding claim 12, Malloug discloses a method [fig. 1] comprising: receiving a square wave [section II. B] having a frequency [fclk/N, section III. A] at an input of a harmonic-cancellation (HC) sine-wave generator [abstract]; receiving a clock signal [Clock] having a clock frequency [fclock] at a clock input [input clk] of the HC sine-wave generator; generating one or more delayed square waves [using 12-Flip-Flops] based on the received square wave and the clock signal using one or more delay components of the HC sine-wave generator; amplitude-scaling the square wave and the one or more delayed square waves [a periodic signal and its scaled and time-shifted versions with opposite time-shifts, has an spectral content which is that of the original periodic signal but scaled by coefficients, section II] using a plurality of taps [1-bit DAC’s and R0/R1/R2] of the HC sine-wave generator to produce a plurality of amplitude-scaled square waves [output of DAC’s and R0, R1 and R2]; adding the plurality of amplitude-scaled square waves using summing circuitry [the node at C] of the HC sine-wave generator to produce a sine wave [sinusoidal output, Vout] having tone at the frequency with suppressed signal strength at selected harmonics of the frequency of the square wave; and providing the sine wave to an output terminal [Vout terminal] of the HC sine-wave generator.
Regarding claim 16, Malloug discloses [fig. 1] filtering the output signal at the output terminal using a resistor-capacitor (RC) filter [RC] coupled to the output terminal.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-9 are rejected under 35 U.S.C. 103 as being unpatentable over Malloug et al. Mostly-digital design of sinusoidal signal generators for mixed-signal BIST applications using harmonic cancellation (NPL cited by Applicants) in view of Koh et al. Finite Delay Response Harmonic Filters (NPL).
Regarding claim 1, Malloug discloses a device [fig. 1] comprises: a harmonic-cancellation (HC) sine-wave generator [abstract] comprising: an input [D input] configured to receive a square wave [section II. B] having a first frequency [fclk/N, section III. A] with first harmonics; a clock input [Clk input] configured to receive a clock signal [Clock] having a clock frequency [fclk]; an output terminal [vout terminal] configured to provide an output signal [vout]; summing circuitry [the node at C; digital architecture based on a ring oscillator to produce time delayed versions of a digital square-wave, a weighting resistor summing network to combine the time-delayed square-wave signals, and a low order analog low-pass filter to cancel high order harmonic components, section I] including a plurality of inputs [output of DAC’s ] and including an output [output of R1/R2/R0] coupled to the output terminal; a plurality of delay elements [12 flip-flop], each delay element including a data input [D], a second input [Clk] coupled to the clock input to receive the clock signal, and an output [Q] to provide a delayed square wave [output of Q]; a plurality of taps [1-bit DAC’s] including a first tap [first 1-bit DAC] and one or more second taps, the first tap [1-bit DAC] first including an input [input receives output Q] coupled to the input to receive the square wave and an output [output 1-bit DAC] to provide an amplitude-scaled square wave [by means of R0, R1…] to a first input of the summing circuitry [input to summing node], each of the one or more second taps [first 1-bit DAC] including an input to receive a delayed square wave [Q] from one of the plurality of delay elements and including an output to provide an amplitude-scaled delayed square wave [by means of R0, R1…] to an associated input of the plurality of inputs of the summing circuitry. Malloug does not explicitly disclose wherein the summing circuitry is configured to add the amplitude-scaled square wave and the one or more amplitude-scaled delayed square waves to produce the output signal including a tone at the first frequency and having suppressed first harmonics at one or more selected frequencies.
However, Koh discloses [see figs. 1a, 1b and 10] a summing circuitry (+, fig. 10) is configured to add the amplitude-scaled (α0, fig. 10) square wave (VLO, fig. 10) and the one or more amplitude-scaled (α1, fig. 10) delayed square waves (delayed using τD, fig. 10) to produce an output signal [vout] including a tone at the first frequency [fundamental tone, section II] and having suppressed first harmonics at one or more selected frequencies. However, Udrea discloses [see fig. 13 and cl. 20, In 66] a PGaN depletion mode device [36]. It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Malloug as taught in Koh in order to suppressed harmonics at one or more selected frequencies.
Regarding claim 2, Malloug in view of Koh discloses [fig. 1] wherein the plurality of delay elements [12 flip-flop] and the plurality of taps [1-bit DAC’s] are configured to produce notches at the selected frequencies.
Regarding claim 3, Malloug in view of Koh discloses [fig. 1] wherein: the clock frequency and coefficients of the plurality of taps determine the selected frequencies of the notches; and one or more of the clock frequency and the coefficients are changed to alter the selected frequencies of the notches.
Regarding claim 4, Malloug in view of Koh discloses [fig. 1] wherein each of the plurality of delay elements comprises a D flip flop [flip-flops].
Regarding claim 5, Malloug in view of Koh discloses [figs. 2 and 3], wherein each of the plurality of taps comprises: a resistor [e.g., r1, fig. 3] including a first terminal coupled to one of the plurality of inputs of the summing circuitry and including a second terminal; and a switch [e.g., M0, fig. 3] including a first terminal coupled to one of the inputs to receive the square wave or one of the output of one of the plurality of delay elements [through RX] to receive the delayed square wave, a second terminal coupled to the second terminal of the resistor, a first supply terminal [terminal first SW, fig. 2] to receive a first reference voltage [V2, fig. 2], and a second supply terminal [terminal second SW, fig. 2] to receive a second reference voltage [V1, fig. 2].
Regarding claim 6, Malloug in view of Koh discloses [figs. 1] wherein the resistors of the plurality of taps have different resistances [R0/R1/R2].
Regarding claim 7, Malloug in view of Koh discloses [figs. 2-3] wherein the switch of each of the plurality of taps comprises: a first transistor [e.g., M0, fig. 2] including a source [source M0] coupled to the first reference voltage, a gate [gate M0] coupled to the one of the input to receive the square wave [indirectly coupled when M0 turn on] or the output of one of the plurality of delay elements to receive the delayed square wave, and a drain coupled [drain M0] to the second terminal of the resistor; and a second transistor [e.g., M1 in second SW, fig. 2] including a source [source M1] coupled to the second reference voltage [V1 in second SW fig. 3], a gate [gate M1] coupled to the gate of the first transistor [indirectly], and a drain [drain M1] coupled to the second terminal of the resistor.
Regarding claim 8, Malloug in view of Koh discloses [fig. 1] wherein the plurality of delay elements includes a sequence of delay elements [12 flip-flop] comprising: a first delay element [first Flip-Flops] including a data input [D] coupled to the input to receive the square wave, a second input [Clk] coupled to the clock input to receive the clock signal, and an output [output from Q] to provide a first delayed square wave [first output from Q] to one of the one or more second taps; one or more second delay elements [second Flip-Flops], each second delay element including an input [second input D] coupled to the output of a previous delay element of the sequence of delay elements, and an output to provide an intermediate delayed square wave [second delay output of Q] to a different one of the one or more second taps; and an N-th delay [third flip-flop] element including a data input [D] coupled to the output of a previous delay element of the sequence, a second input [second Clk input] coupled to the clock input, and an output [second output of Q] to provide an n-th delayed square wave to an n-th tap of the one or more second taps.
Regarding claim 9, Malloug in view of Koh discloses [fig. 1] further comprising a resistor-capacitor (RC) filter [RC] coupled to the output terminal.
Claims 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Malloug et al. in view of Soh (US 2002/0196865).
Regarding claim 17, Malloug discloses a device [fig. 1] comprising: a first harmonic-cancellation (HC) sine-wave generator [fig. 1, abstract] including: a first input [D input] to receive a first square wave [section II. B] having a first frequency [fclk/N, section III. A]; a second input [Clk input] to receive a first clock signal [Clock] having a first clock frequency [fclk]; an output terminal [vout terminal]; first delay elements [12 flip-flop] in a sequence configured to receive the first square wave and the first clock signal and to produce one or more first delayed square waves [second output Q]; one or more first taps [first 1-bit DAC and R2] configured to produce first amplitude-scaled square waves based on the first square wave and the one or more first delayed square waves. Malloug does not explicitly disclose one or more second HC sine-wave generators, each of the one or more second HC sine-wave generators including: a first input to receive a second square wave having a second frequency; a second input to receive a second clock signal having a second clock frequency; one or more second delay elements in a sequence and configured to receive the second square wave and the second clock signal and to produce one or more second delayed square waves; one or more second taps configured to produce second amplitude-scaled square waves based on the second square wave and the one or more second delayed square waves and to produce the one or more second amplitude-scaled square waves; and summing circuitry configured to add the first amplitude-scaled square waves and one or more of the second amplitude-scaled square waves from the one or more second HC sine-wave generators to produce a sine wave having a first tone at the first frequency and one or more second tones at the one or more second frequencies and including suppressed energy at selected harmonics of the first frequency and the one or more second frequencies, the summing circuitry to provide the sine wave to the output terminal.
However, Soh discloses [fig. 2] one or more second HC sine-wave generators [e.g., 201/211/221 or 202/212/222] and summing circuitry [e.g., 242] configured to add the first amplitude-scaled square waves [231] and one or more of the second amplitude-scaled square waves from the one or more second HC sine-wave generators to produce a sine wave [e.g., 292] having a first tone at the first frequency [e.g., frequency 201] and one or more second tones at the one or more second frequencies [e.g., frequency at 202] and including suppressed energy at selected harmonics of the first frequency and the one or more second frequencies, the summing circuitry to provide the sine wave to the output terminal [terminal 290].
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Malloug by incorporate the second HC sine-wave generators as taught in Soh. Soh teaches providing both first and second HC sine-wave generators and summing circuitry, and a person of ordinary skill would have found it obvious to replicate the HC sine-wave generator of Malloug, fig. 1 (which already includes a first input [D] to receive a second square wave [section II. B] having a second frequency [fclk/N, section III. A]; a second input [input Clk] to receive a second clock signal [clock] having a second clock frequency [fclk]; one or more second delay elements [12 Flip-Flops] in a sequence and configured to receive the second square wave [second input D] and the second clock signal and to produce one or more second delayed square waves [second output from Q]; one or more second taps [second 1-bit DAC and R1] configured to produce second amplitude-scaled square waves based on the second square wave and the one or more second delayed square waves and to produce the one or more second amplitude-scaled square waves) to form a second HC sine-wave generator, consistent with a plurality of sine-wave generators as taught in Soh, would have been a predictable use of known circuit duplication techniques in order to provide a continuous shaped waveform.
Regarding claim 18, Malloug in view of Soh disclose [fig. 1] wherein: the one or more first taps include one or more first resistors [e.g. R2] coupled to the summing circuitry, the one or more first resistors define a first set of coefficients [α1] for the one or more first taps; the one or more second taps including one or more second resistors [e.g., R1] coupled to the summing circuitry, the one or more second resistors define one or more second sets of coefficients [α2] for the one or more second taps; and one or more of the first clock frequency, the one or more second clock frequencies, the first set of coefficients, or the one or more second sets of coefficients are different to produce first notches [the first harmonic that is cancelled] at first selected harmonics of the first frequency and second notches [second harmonic that is cancelled] at second selected harmonics of the one or more second frequencies.
Regarding claim 19, Malloug in view of Soh disclose [fig. 2] wherein the first clock frequency (f0) and the one or more second clock frequencies are the same and a first set of coefficients of the first HC sine-wave generator and one or more second sets of coefficients of the one or more second HC sine-wave generators are different.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Malloug et al. in view of Soh further in view of Park et al. (US 2018/0091123 and Park hereinafter).
Regarding claim 20, Malloug in view of Koh teaches all the features with respect to claim 17 as outlined above. Malloug in view of Koh does not disclose wherein the first clock frequency and the one or more second clock frequencies are different, and a first set of coefficients of the first HC sine-wave generator and one or more second sets of coefficients of the one or more second HC sine-wave generators are different.
However, Park discloses [fig. 1] wherein a first clock frequency [1st square wave frequency] and the one or more second clock frequencies [2nd square wave (3 times higher frequency)] are different, and a first set of coefficients of the first HC sine-wave generator and one or more second sets of coefficients of the one or more second HC sine-wave generators are different [par. 0033-41]. It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Malloug/Koh by incorporate the different frequencies and coefficients in order provide harmonic-controlled, high-quality sine waves that can make a contribution to improving the functions of various controllers [par. 0021].
Claims 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Malloug et al. in view of Koh et al. further in view of Soh.
Regarding claim 10, Malloug in view of Koh teaches all the features with respect to claim 1 as outlined above. Malloug in view of Koh does not disclose a second HC sine-wave generator comprising: a second input configured to receive a second square wave having a second frequency with second harmonics; a second clock input configured to receive a second clock signal having a second clock frequency; a second plurality of delay elements, each delay element including a data input, a second input coupled to the second clock input to receive the second clock signal, and an output to provide a delayed second square wave; a second plurality of taps including a first tap and one or more second taps, the first tap including an input coupled to the second input to receive the second square wave and an output to provide an amplitude-scaled second square wave to the first input of the summing circuitry, each of the one or more second taps including an input to receive a delayed second square wave from one of the second plurality of delay elements and including an output to provide an amplitude-scaled delayed second square wave to an associated input of the plurality of inputs of the summing circuitry; and wherein the summing circuitry is configured to add the amplitude-scaled square wave, the amplitude-scaled second square wave, the one or more amplitude-scaled delayed square waves, and the one or more amplitude-scaled delayed second square waves to produce the output signal including the tone at the first frequency, a second tone at the second frequency, and the one or more suppressed harmonics at the one or more selected frequencies and at one or more second selected frequencies.
However, Soh discloses [fig. 2] one or more second HC sine-wave generators [e.g., 201/211/221 or 202/212/222] and summing circuitry [e.g., 242] configured to add the first amplitude-scaled square waves [231] and one or more of the second amplitude-scaled square waves from the one or more second HC sine-wave generators to produce a sine wave [e.g., 292] including the tone at the first frequency, a second tone at the second frequency, and the one or more suppressed harmonics at the one or more selected frequencies and at one or more second selected frequencies.
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Malloug in view of Koh by incorporate the second HC sine-wave generators as taught in Soh. Soh teaches providing both first and second HC sine-wave generators and summing circuitry, and a person of ordinary skill would have found it obvious to replicate the HC sine-wave generator of Malloug/Koh of fig. 1 (which already includes a second input [input D] configured to receive a second square wave [section II. B] having a second frequency [[fclk/N, section III. A]] with second harmonics; a second clock input [clk input] configured to receive a second clock signal [clock] having a second clock frequency [fclk]; a second plurality of delay elements [12 Flip-flops], each delay element including a data input [D input], a second input [clk input] coupled to the second clock input to receive the second clock signal, and an output [output Q] to provide a delayed second square wave [delayed output square wave from Q]; a second plurality of taps [1-bit DAC’s and R2, R1 and R0] including a first tap [first 1-bit DAC and R2] and one or more second taps [second 1-bit DAC and R1], the first tap including an input [input to receive output Q] coupled to the second input to receive the second square wave and an output [Vout] to provide an amplitude-scaled second square wave to the first input of the summing circuitry, each of the one or more second taps including an input [input to D] to receive a delayed second square wave [output Q] from one of the second plurality of delay elements and including an output [output Q] to provide an amplitude-scaled delayed second square wave to an associated input of the plurality of inputs of the summing circuitry [the node at C] wherein the summing circuitry [see ref, Koh fig. 1] is configured to add the amplitude-scaled square wave [α1] and the one or more amplitude-scaled delayed square waves [α2]) to form a second HC sine-wave generator, consistent with a plurality of sine-wave generators as taught in Soh, would have been a predictable use of known circuit duplication techniques in order to provide a continuous shaped waveform.
Regarding claim 11, Malloug in view of Koh further in view of Soh discloses [fig. 1] wherein the clock frequency and the second clock frequency are the same and a first set of coefficients of the plurality of taps is different from a second set of coefficients of the second plurality of taps.
Claims 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Malloug et al. in view of Soh.
Regarding claim 13, Malloug teaches all the features with respect to claim 12 as outlined above. Malloug does not disclose receiving a second square wave having a second frequency at an input of a second HC sine-wave generator; receiving a second clock signal having a second clock frequency at a clock input of the second HC sine-wave generator; generating one or more delayed second square waves based on the received second square wave and the second clock signal using one or more delay components of the second HC sine-wave generator; and amplitude-scaling the second square wave and the one or more delayed second square waves using a plurality of taps of the second HC sine-wave generator to produce a second plurality of amplitude-scaled square waves.
However, Soh discloses [fig. 2] a second square wave [e.g., 201/202/203/204] having a second frequency [e.g., frequency 201/202/203/204] at an input of a second HC sine-wave generators [e.g., 211~214, 221-224]. It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Malloug by incorporate the second HC sine-wave generators as taught in Soh. Soh teaches providing both first and second HC sine-wave generator, and a person of ordinary skill would have found it obvious to replicate the HC sine-wave generator of Malloug of fig. 1 (which already includes receiving a second clock signal [clock] having a second clock frequency [fclk] at a clock input of the second HC sine-wave generator; generating one or more delayed second square waves [output of Q] based on the received second square wave and the second clock signal using one or more delay components of the second HC sine-wave generator; and amplitude-scaling the second square wave and the one or more delayed second square waves using a plurality of taps [1-bit DAC’s and R0/R1/R2] of the second HC sine-wave generator to produce a second plurality of amplitude-scaled square waves [output of 1-bit DAC’s and R0/R1/R2]) to form a second HC sine-wave generator, consistent with a plurality of sine-wave generators as taught in Soh, would have been a predictable use of known circuit duplication techniques in order to provide a continuous shaped waveform.
Regarding claim 14, Malloug in view of Soh discloses [see fig. 2, Soh] adding [using 242] the plurality of amplitude-scaled square waves [231] and the second plurality of amplitude-scaled square waves [232] to produce the output signal [252]; and wherein the output signal includes the tone corresponding to the frequency of the square wave [frequency 231] and a second tone corresponding to the second frequency of the second square wave [frequency 232] and including the suppressed signal strength at the selected harmonics of the frequency of the square wave and the second frequency of the second square wave.
Regarding claim 15, Malloug in view of Soh discloses further comprising adjusting one or more of the clock frequency, the second clock frequency, or one or more coefficients associated with the plurality of taps to adjust selected frequencies of notches configured to suppress the selected harmonics of the frequency of the square wave and the second frequency of the second square wave.
Conclusion
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/METASEBIA T RETEBO/ Primary Examiner, Art Unit 2842