DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-5, 11 and 13-20 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-11 of copending Application No. 18/789,751 in view of Inazuka et al. (US Publication 2015/0116896) and in further view of Ichiro et al. (JP2019004097A).
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Figure 2 of Inazuka with Examiner’s Comments (Figure 2EC)
In re claim 1, Application No. 18/789,751 discloses a multilayer body including a plurality of dielectric layers that are laminated, a first main surface and a second main surface opposed to each other in a lamination direction, a first lateral surface and a second lateral surface opposed to each other in a width direction orthogonal or substantially orthogonal to the lamination direction, and a first end surface and a second end surface opposed to each other in a length direction orthogonal or substantially orthogonal to the lamination direction and the width direction (Claim 1);
a plurality of first internal electrode layers each on a corresponding one of the plurality of dielectric layers and each exposed at the first end surface (Claim 1);
a plurality of second internal electrode layers each on a corresponding one of the plurality of dielectric layers and each exposed at the second end surface (Claim 1);
a first external electrode on the first end surface and connected to the plurality of first internal electrode layers (Claim 1); and
a second external electrode on the second end surface and connected to the plurality of second internal electrode layers (Claim 1);
wherein each of the plurality of first internal electrode layers includes a first counter portion opposed to a corresponding one of the plurality of second internal electrode layers and a first extension portion extending from the first counter portion toward the first end surface and exposed at the first end surface (Claim 1);
each of the plurality of second internal electrode layers includes a second counter portion opposed to a corresponding one of the plurality of first internal electrode layers and a second extension portion extending from the second counter portion toward the second end surface and exposed at the second end surface (Claim 1);
the first counter portion includes:
a first region adjacent to the first end surface;
a second region adjacent to the second end surface; and
a first middle region between the first region and the second region, and including coverage higher than coverage of the first region and the second region (Claim 1),
the second counter portion includes:
a third region adjacent to the second end surface;
a fourth region adjacent to the first end surface (Claim 1);
a second middle region between the third region and the fourth region and having higher coverage than the coverage of the third region and the coverage of the fourth region (Claim 1).
U.S. Application 18/789,751 does not disclose each of the plurality of first internal electrode layers further includes a first sloped portion coupling the first region and the first middle region and a second sloped portion coupling the second region and the first middle region and each of the plurality of second internal electrode layers further includes a third sloped portion coupling the third region and the second middle region, and a fourth sloped portion coupling the fourth region and the second middle region.
Inazuka discloses each of the plurality of first internal electrode layers further includes a first sloped portion (4 connected to 5a within S1 – Figure 2EC) coupling the first region and the first middle region and a second sloped portion (4 connected to 51 within S2 – Figure 2EC) coupling the second region and the first middle region (Figure 2EC); and
each of the plurality of second internal electrode layers further includes a third sloped portion (4 connected to 5b within S2 – Figure 2EC) coupling the third region and the second middle region, and a fourth sloped portion (4 connected to 5b within S1 – Figure 2EC) coupling the fourth region and the second middle region (Figure 5EC).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the sloped internal electrodes as described by Inazuka to provide for a capacitor having reduced occurrence of delamination (¶61: Inazuka).
U.S. Application 18/789,751 does not disclose a first middle region having higher coverage than a coverage of the first region and a coverage of the second region, and a second middle region having higher coverage than the coverage of the third region and the coverage of the fourth region
Ichiro discloses a first middle region having higher coverage than a coverage of the first region and a coverage of the second region, and a second middle region having higher coverage than the coverage of the third region and the coverage of the fourth region (Figure 2, Figure 3; 18a3 [40, 42, 44 – Figure 2, Figure 3, ¶31] has higher coverage than the remaining counter electrode region [22a – Figure 2, Figure 4, ¶27]).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the thickness, and thus, coverage, teachings of Ichiro to achieve a device having improved heat dissipation characteristics (¶36: Ichiro).
U.S. Application 18/795,532
U.S. Application 18/789,751
Claim 2
Claim 1
Claim 3
Claim 1
Claim 4
Claim 1, Claim 2
Claim 5
Claim 3
Claim 13
Claim 4
Claim 14
Claim 5
Claim 15
Claim 6
Claim 16
Claim 7
Claim 17
Claim 8
Claim 18
Claim 9
Claim 19
Claim 10
Claim 20
Claim 11
In re claim 11, U.S. Application 18/789,751 in view of Inazuka in view of Ichiro discloses the multilayer ceramic capacitor according to claim 1, as explained above. U.S. Application 18/789,751 does not disclose wherein a length in the length direction of the first sloped portion and a length in the length direction of the second sloped portion are shorter than a length in the length direction of the first middle region; and
a length in the length direction of the third sloped portion and a length in the length direction of the fourth sloped portion are shorter than a length in the length direction of the second middle region.
Inazuka discloses wherein a length in the length direction of the first sloped portion (4 connected to 5a in S1 – Figure 2EC) and a length in the length direction of the second sloped portion (4 connected to 5a in S2 – Figure 2EC) are shorter than a length in the length direction of the first middle region (4 connected to 5a in RM – Figure 2EC); and
a length in the length direction of the third sloped portion (4 connected to 5b in S2 – Figure 2EC) and a length in the length direction of the fourth sloped portion (4 connected to 5b in S1 – Figure 2EC) are shorter than a length in the length direction of the second middle region (4 connected to 5b in RM – Figure 2EC).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the sloped internal electrodes as described by Inazuka to provide for a capacitor having reduced occurrence of delamination (¶61: Inazuka).
Claims 6-7 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of copending Application No. 18/789,751 in view of Inazuka et al. (US Publication 2015/0116896) and in further view of Ichiro et al. (JP2019004097A) and in further view of Sakai (US Publication 2015/0116902).
In re claim 6, U.S. Application 18/789,751 in view of Inazuka and in further view of Ichiro discloses the multilayer ceramic capacitor according to claim 1, as explained above. Inazuka does not disclose wherein the plurality of first internal electrode layers each further include a fifth sloped portion located at the first extension portion; and the plurality of second internal electrode layers each further include a sixth sloped portion located at the second extension portion.
Sakai discloses wherein the plurality of first internal electrode layers (5a – Figure 1B, ¶35) each further include a fifth sloped portion (6 – Figure 1B, ¶35) located at the first extension portion (Figure 1B); and
the plurality of second internal electrode (5b – Figure 1B, ¶35) layers each further include a sixth sloped portion (6 – Figure 1B) located at the second extension portion (Figure 1B).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the sloped portions of Sakai to increase the adhesion between the internal electrodes and dielectric layers (¶36: Sakai).
In re claim 7, U.S. Application 18/789,751 in view of Inazuka in view of Ichiro and in further view of Sakai discloses the multilayer ceramic capacitor according to claim 6, as explained above. Inazuka does not disclose wherein a slope angle of each of the first sloped portion and the second sloped portion is smaller than a slope angle of the fifth sloped portion; and a slope angle of each of the third sloped portion and the fourth sloped portion is smaller than a slope angle of the sixth sloped portion.
Sakai discloses that increasing the slope angle of the fifth and sixth sloped portions (6 – Figure 1B) is directly correlated to an enhanced wedge effect, and thus, increase in adhesion properties between the internal electrodes and dielectric layers (¶35-36: Sakai). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to increase the slope angle of the lead-out sloped portions to achieve a device having desired mechanical strength, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
This is a provisional nonstatutory double patenting rejection.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 11, 13, 14-16, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Inazuka et al. (US Publication 2015/0116896) in view of Ichiro et al. (JP2019004097A).
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Figure 2 of Inazuka with Examiner’s Comments (Figure 2EC)
In re claim 1, Inazuka discloses a multilayer ceramic capacitor comprising:
a multilayer body (2 – Figure 2, ¶33) including a plurality of dielectric layers (3 – Figure 2, ¶33) that are laminated, a first main surface (2a1 – Figure 2, ¶41) and a second main surface (2a2 – Figure 2, ¶41) opposed to each other in a lamination direction (‘T’ direction - Figure 2, Figure 1), a first lateral surface (2c1 – Figure 3, Figure 1, ¶41) and a second lateral surface (2c2 – Figure 3, Figure 1, ¶41) opposed to each other in a width direction (‘W’ direction – Figure 1, Figure 3) orthogonal or substantially orthogonal to the lamination direction (Figure 1, Figure 3), and a first end surface (2b1 – Figure 2, Figure 1, ¶41) and a second end surface (2b2 – Figure 2, Figure 1, ¶41) opposed to each other in a length direction (‘L’ direction – Figure 2, Figure 1) orthogonal or substantially orthogonal to the lamination direction and the width direction (Figure 1);
a plurality of first internal electrode layers (4 connected to 2b1 – Figure 2, ¶48) each on a corresponding one of the plurality of dielectric layers (3 – Figure 2) and each exposed at the first end surface (2b1 – Figure 2);
a plurality of second internal electrode layers (4 connected to 2b2 – Figure 2) each on a corresponding one of the plurality of dielectric layers (3 – Figure 2) and each exposed at the second end surface (2b2 – Figure 2);
a first external electrode (5a – Figure 2, ¶32) on the first end surface (2b1 – Figure 2) and connected to the plurality of first internal electrode layers (Figure 2); and
a second external electrode (5b – Figure 2, ¶32) on the second end surface (2b2 – Figure 2) and connected to the plurality of second internal electrode layers (Figure 2);
wherein each of the plurality of first internal electrode layers includes a first counter portion (4 connected to 2b1 within 9 – Figure 2, ¶67) opposed to a corresponding one of the plurality of second internal electrode layers (4 connected to 2b2 – Figure 2) and a first extension portion (4c1 – Figure 4, Figure 2, ¶38) extending from the first counter portion toward the first end surface and exposed at the first end surface (Figure 4, Figure 2);
each of the plurality of second internal electrode layers includes a second counter portion (4 connected to 2b2 within 9 – Figure 2) opposed to a corresponding one of the plurality of first internal electrode layers and a second extension portion (4c2 – Figure 5, ¶38) extending from the second counter portion toward the second end surface and exposed at the second end surface (Figure 4, Figure 2);
the first counter portion includes:
a first region (4 connected to 5a within R1 – Figure 2EC) adjacent to the first end surface (2b1 – Figure 2EC);
a second region (4 connected to 5a within R2 – Figure 2EC) adjacent to the second end surface (2b2 – Figure 2EC); and
a first middle region (4 connected to 5a within RM – Figure 2EC) between the first region and the second region (Figure 2EC), located closer to an outside of the multilayer body than the first region and the second region in the lamination direction (Figure 2EC; Note that the central portion of the inner electrode is at least slightly closer to 2a1 in Figure 2),
the second counter portion includes:
a third region (4 connected to 5b within R2 – Figure 2EC) adjacent to the second end surface (2b2 – Figure 2EC);
a fourth region (4 connected to 5b within R1 – Figure 2EC) adjacent to the first end surface (2b1 – Figure 2EC); and
a second middle region (4 connected to 5b within RM – Figure 2EC) between the third region and the fourth region (Figure 2EC), located closer to an outside of the multilayer body than the third region and the fourth region in the lamination direction, (Figure 2EC; Note that the central portion of the inner electrode is at least slightly closer to 2a1 in Figure 2);
each of the plurality of first internal electrode layers further includes a first sloped portion (4 connected to 5a within S1 – Figure 2EC) coupling the first region and the first middle region and a second sloped portion (4 connected to 51 within S2 – Figure 2EC) coupling the second region and the first middle region (Figure 2EC); and
each of the plurality of second internal electrode layers further includes a third sloped portion (4 connected to 5b within S2 – Figure 2EC) coupling the third region and the second middle region, and a fourth sloped portion (4 connected to 5b within S1 – Figure 2EC) coupling the fourth region and the second middle region (Figure 5EC).
Inazuka does not disclose a first middle region having higher coverage than a coverage of the first region and a coverage of the second region, and a second middle region having higher coverage than the coverage of the third region and the coverage of the fourth region
Ichiro discloses a first middle region having higher coverage than a coverage of the first region and a coverage of the second region, and a second middle region having higher coverage than the coverage of the third region and the coverage of the fourth region (Figure 2, Figure 3; 18a3 [40, 42, 44 – Figure 2, Figure 3, ¶31] has higher coverage than the remaining counter electrode region [22a – Figure 2, Figure 4, ¶27]).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the thickness, and thus, coverage, teachings of Ichiro to achieve a device having improved heat dissipation characteristics (¶36: Ichiro).
In re claim 2, Inazuka in view of Ichiro discloses the multilayer ceramic capacitor according to claim 1, as explained above. Inazuka further discloses wherein a length of the first middle region (4 connected to 5a in RM – Figure 2EC) in the length direction (‘L’ direction – Figure 2EC) is shorter than a distance between the first external electrode (5a – Figure 2EC) and the second external electrode (5b – Figure 2EC); and
a length of the second middle region (4 connected to 5b in RM – Figure 2EC) in the length direction (‘L’ direction – Figure 2EC) is shorter than the distance between the first external electrode (5a – Figure 2EC) and the second external electrode (5b – Figure 2EC).
In re claim 3, Inazuka in view of Ichiro discloses the multilayer ceramic capacitor according to claim 1, as explained above. Inazuka further discloses wherein the multilayer body (2 – Figure 2) includes exposed portions (2a1, 2a2 between 5a,5b – Figure 2) each exposed from the first external electrode and the second external electrode (Figure 2), first covered portions (2a1, 2a2 covered by 5a– Figure 2) portions of each covered by the first external electrode (5a – Figure 2), and second covered portions (2a1, 2a2 covered by 5b – Figure 2) each covered by the second external electrode (5b – Figure 2); and
a distance in the lamination direction at a center of each of the exposed portions in the length direction is longer than a maximum distance in the lamination direction between surfaces (2b1, 2b2 – Figure 2) adjacent to the first main surface and the second main surface (2a1, 2a2 – Figure 2) of each of the first covered portions and the second covered portions (Figure 2), and shorter than a maximum distance in the lamination direction between a first main surface-side surface and a second main surface-side surface of each of the first external electrode and the second external electrode (distance between 5a on 2a1 and 5a on 2a2, distance between 5b on 2a1 and 5b on 2a2 – Figure 2), the first main surface-side surface and the second main surface-side surface each functioning as an outermost surface and being exposed to outside (Figure 2).
In re claim 4, Inazuka in view of Ichiro discloses the multilayer ceramic capacitor according to claim 1, as explained above. Inazuka further discloses wherein the first main surface (2a1 – Figure 2) includes a first exposed surface (2a1 exposed from 5a, 5b – Figure 2) exposed from the first external electrode and the second external electrode (5a, 5b – Figure 2), a first covered surface (2a1 covered by 5a – Figure 2) covered by the first external electrode, and a second covered surface (2a2 covered by 5b – Figure 2) covered by the second external electrode; and
the first exposed surface includes a first flat surface parallel or substantially parallel to the lamination direction (Figure 2; Note that the center region of 2a1, 2a2 is flat for a span of a small region.), a first sloped surface coupling the first flat surface and the first covered surface, and a second sloped surface coupling the first flat surface and the second covered surface (Figure 2; Note that the first and second sloped surfaces are disposed on either side of the flat surface in the ‘L’ direction.).
In re claim 11, Inazuka in view of Ichiro discloses the multilayer ceramic capacitor according to claim 1, as explained above. Inazuka further discloses wherein a length in the length direction of the first sloped portion (4 connected to 5a in S1 – Figure 2EC) and a length in the length direction of the second sloped portion (4 connected to 5a in S2 – Figure 2EC) are shorter than a length in the length direction of the first middle region (4 connected to 5a in RM – Figure 2EC); and
a length in the length direction of the third sloped portion (4 connected to 5b in S2 – Figure 2EC) and a length in the length direction of the fourth sloped portion (4 connected to 5b in S1 – Figure 2EC) are shorter than a length in the length direction of the second middle region (4 connected to 5b in RM – Figure 2EC).
In re claim 13, Inazuka in view of Ichiro discloses the multilayer ceramic capacitor according to claim 1, as explained above. Inazuka further discloses wherein a dimension of the multilayer body in the length direction is about 0.2 mm or more and about 6 mm or less (¶95);
a dimension of the multilayer body in the lamination direction is about 0.05 mm or more and about 5 mm or less (¶95); and
a dimension of the multilayer body in the width direction is about 0.1 mm or more and about 5 mm or less (¶95).
In re claim 14, Inazuka in view of Ichiro discloses the multilayer ceramic capacitor according to claim 1, as explained above. Inazuka further discloses wherein each of the plurality of dielectric layers includes BaTiO3, CaTiO3, SrTiO3, or CaZrO3 as a main component (¶35).
In re claim 15, Inazuka in view of Ichiro discloses the multilayer ceramic capacitor according to claim 14, as explained above. Inazuka further discloses wherein each of the plurality of dielectric layers includes a Mn compound, an Fe compound, a Cr compound, a Co compound, or a Ni compound as a secondary component (¶33).
In re claim 16, Inazuka in view of Ichiro discloses the multilayer ceramic capacitor according to claim 1, as explained above. Inazuka does not explicitly disclose a thickness of each of the plurality of dielectric layers is about 0.2 μm or more and about 10 μm or less. However, it is well-known in the art that adjusting the thickness of the dielectric layer is directly correlated to the capacitance of the device. It would have been an obvious matter of design choice to adjust the thickness of the dielectric layers to achieve a device of desired capacitance, since such a modification would have involved a mere change in the size of a component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
In re claim 18, Inazuka in view of Ichiro discloses the multilayer ceramic capacitor according to claim 1, as explained above. Inazuka further discloses wherein each of the plurality of first and second internal electrodes includes Ni, Cu, Ag, Pd or Au, or an alloy including at least one of Ni, Cu, Ag, Pd or Au (¶33).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Inazuka et al. (US Publication 2015/0116896) in view Ichiro et al. (JP2019004097A) and in further view of Mizuno (US Publication 2017/0250026).
In re claim 5, Inazuka in view of Ichiro discloses the multilayer ceramic capacitor according to claim 4, as explained above. Inazuka does not disclose wherein a length of the first sloped surface in the length direction and a length of the second sloped surface in the length direction are shorter than a length of the first flat surface in the length direction.
Mizuno discloses wherein a length of the first sloped surface (f6a – Figure 6, ¶31) in the length direction and a length of the second sloped surface (f6b – Figure 6, ¶31) in the length direction are shorter than a length of the first flat surface (f6 – Figure 6, ¶31) in the length direction (Figure 6).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the tapered surface as described by Mizuno to increase mechanical strength between the external electrodes and component body (¶10: Mizuno).
Claim(s) 6-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Inazuka et al. (US Publication 2015/0116896) in view Ichiro et al. (JP2019004097A) and in further view of Sakai (US Publication 2015/0116902).
In re claim 6, Inazuka in view of Ichiro discloses the multilayer ceramic capacitor according to claim 1, as explained above. Inazuka does not disclose wherein the plurality of first internal electrode layers each further include a fifth sloped portion located at the first extension portion; and the plurality of second internal electrode layers each further include a sixth sloped portion located at the second extension portion.
Sakai discloses wherein the plurality of first internal electrode layers (5a – Figure 1B, ¶35) each further include a fifth sloped portion (6 – Figure 1B, ¶35) located at the first extension portion (Figure 1B); and
the plurality of second internal electrode (5b – Figure 1B, ¶35) layers each further include a sixth sloped portion (6 – Figure 1B) located at the second extension portion (Figure 1B).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the sloped portions of Sakai to increase the adhesion between the internal electrodes and dielectric layers (¶36: Sakai).
In re claim 7, Inazuka in view of Ichiro and in further view of Sakai discloses the multilayer ceramic capacitor according to claim 6, as explained above. Inazuka does not disclose wherein a slope angle of each of the first sloped portion and the second sloped portion is smaller than a slope angle of the fifth sloped portion; and a slope angle of each of the third sloped portion and the fourth sloped portion is smaller than a slope angle of the sixth sloped portion.
Sakai discloses that increasing the slope angle of the fifth and sixth sloped portions (6 – Figure 1B) is directly correlated to an enhanced wedge effect, and thus, increase in adhesion properties between the internal electrodes and dielectric layers (¶35-36: Sakai). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to increase the slope angle of the lead-out sloped portions to achieve a device having desired mechanical strength, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Claim(s) 17 and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Inazuka et al. (US Publication 2015/0116896) in view Ichiro et al. (JP2019004097A) and in further view of Katsube et al. (US Publication 2023/0126382).
In re claim 17, Inazuka in view of Ichiro discloses the multilayer ceramic capacitor according to claim 1, as explained above. Inazuka does not explicitly disclose wherein a number of the plurality of dielectric layers is fifteen or more and 1200 or less.
Katsube discloses wherein a number of the plurality of dielectric layers is fifteen or more and 1200 or less (¶67).
It would have been obvious to a person having ordinary skill in the art before the effective filing date to adjust the number of dielectric layers to achieve a device of desired capacitance, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
In re claim 19, Inazuka in view of Ichiro discloses the multilayer ceramic capacitor according to claim 1, as explained above. Inazuka does not disclose wherein a thickness of each of the plurality of first and second internal electrodes is about 0.2 μm or more and about 2.0 μm or less.
Katsube discloses a thickness of each of the plurality of first and second internal electrodes is about 0.2 μm or more and about 2.0 μm or less (¶92).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the internal electrode thickness as described by Katsube to provide for an electronic component having desired ESR characteristics.
In re claim 20, Inazuka in view of Ichiro discloses the multilayer ceramic capacitor according to claim 1, as explained above. Inazuka does not disclose wherein a number of the plurality of first and second internal electrodes is fifteen or more and 1000 or less.
Katsube discloses wherein a number of the plurality of first and second internal electrodes is fifteen or more and 1000 or less (¶93).
It would have been obvious to a person having ordinary skill in the art before the effective filing date to adjust the number of internal electrode layers to achieve a device of desired capacitance, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Allowable Subject Matter
Claims 8-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The prior art does not teach nor suggest (in combination with other claim limitations) a step distance in the lamination direction between the first region and the first middle region generated by the first sloped portion is greater than a thickness of one of the plurality of dielectric layers provided between the first internal electrode layer and the second internal electrode layer in the lamination direction, and a step distance in the lamination direction between the third region and the second middle region generated by the third sloped portion is greater than a thickness of one of the plurality of dielectric layers provided between the first internal electrode layer and the second internal electrode layer in the lamination direction.
Claims 10 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The prior art does not teach nor suggest (in combination with other claim limitations) the first middle region, the first region, the second region, the second middle region, the third region, and the fourth region each include a portion parallel or substantially parallel to a plane orthogonal or substantially orthogonal to the lamination direction.
Claims 12 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The prior art does not teach nor suggest (in combination with other claim limitations) a thickness of the first and fourth sloped portions gradually decreases towards the first end surface, and a thickness of the second and third sloped portions gradually decreases toward the second end surface.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kan et al. (US Publication 2017/0162330) Figure 4C, Figure 4D
Tanaka (US Publication 2021/0166874) Figure 6
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ARUN RAMASWAMY whose telephone number is (571)270-1962. The examiner can normally be reached Monday - Friday, 9:00 am - 5:00 pm.
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/ARUN RAMASWAMY/Primary Examiner, Art Unit 2848
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