DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1, 7-8, 12-13 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Uhrenholt U.S. Patent Application 20220027283 in view of Kazakov U.S. Patent Application 20190066352.
Regarding claim 1, Uhrenholt discloses an apparatus, comprising:
shader processor circuitry (graphics processor) configured to execute a graphics shader program (paragraph [0125]: the encoding may be performed by a shader core of the (e.g. graphics) processor; paragraph [0163]: the graphics processor (processing pipeline) also comprises one or more programmable shading stages);
cache circuitry (cache) coupled to the shader processor circuitry and configured to store graphics data that includes a compressed block of data and metadata for the compressed block of data (paragraph [0028]: when a block of data that is stored in the memory in a compressed form is to be loaded into the cache, the compressed block of data having a set of associated compression metadata: [0029] storing the block of data into a group of one or more cache lines of the cache); and configured to;
cache the metadata for the compressed block of data; receive an indication of a write command for non-compressed data associated with the surface, wherein the write command identifies the metadata and has a different address than the compressed block of data (paragraph [0030]: providing the compression metadata for the block of data as separate side (different address) band data associated with a cache line of the group of one or more cache lines of the cache in which the block of data is stored; paragraph [0246]: As shown in FIG. 9, on the other hand, in the event that any of the lines read from the cache are “dirty” (indication) (i.e. the L2 cache 24 is storing modified data for the data block such that the data for the data block needs to be written back to the memory system 6); paragraph [0251]: the data encoder will write the uncompressed data for the block read from the L2 cache back to the memory system, with any data for the block that was not present in the L2 cache simply being left “as is” in the memory system 6); and
determine, based on the metadata and the indication, to invalidate the compressed block of data in the cache circuitry (paragraph [0151]: The eviction (write-back) process may in an embodiment comprise checking if any of the data (cache lines) to be read (evicted) have been modified (are “dirty”). If not, then the write-back operation is in an embodiment not performed, and the lines selected for eviction are simply invalidated so as to make them available for reuse).
Uhrenholt discloses all the features with respect to claim 1 as outlined above. However, Uhrenholt fails to disclose block of data associated with a surface, metadata coherence circuitry coupled to the cache circuitry.
Kazakov discloses block of data associated with a surface (paragraph [0050]: a shader can sample the entries 705, 710, 715 within a sampling footprint 720 to determine a residency status or a sampling status of the corresponding tile in the texture associated with the metadata surface 700);
metadata coherence circuitry coupled to the cache circuitry (paragraph [0048]: a cache coherency protocol can be used to modify the cached value of the encoded metadata).
Therefore, it would have been obvious before the effective filing date of the claimed invention to combine Uhrenholt’s to use cache coherency protocol as taught by Kazakov, to save memory resource and reduce overhead.
Regarding claim 7, Uhrenholt as modified by Kazakov discloses the apparatus of claim 1, wherein the shader processor circuitry is configured to determine relationships between portions of a given surface and the corresponding metadata based on a base address of the surface and a base address of the corresponding metadata (Kazakov’s paragraph [0050]: a shader can sample the entries 705, 710, 715 within a sampling footprint 720 to determine a residency status or a sampling status of the corresponding tile in the texture associated with the metadata surface 700; paragraph [0032]: the pipeline 355 can generate a request that contains both a metadata address for a tile and data address for texture data within a tile).
Therefore, it would have been obvious before the effective filing date of the claimed invention to combine Uhrenholt’s to use cache coherency protocol as taught by Kazakov, to save memory resource and reduce overhead.
Regarding claim 8, Uhrenholt as modified by Kazakov discloses the apparatus of claim 1, wherein coherency controller circuitry is configured to store and access metadata information for different portions of a surface in multiple different metadata caches (Kazakov’s paragraph [0030]: The metadata 330 indicates the residency status of a corresponding texture block 310; Uhrenholt’s paragraph [0195]: In both FIGS. 3 and 4, the L2 cache 24 is shown as being configured as respective separate physical cache portions (slices) 30).
Therefore, it would have been obvious before the effective filing date of the claimed invention to combine Uhrenholt’s to use cache coherency protocol as taught by Kazakov, to save memory resource and reduce overhead.
Regarding claim 12, Uhrenholt as modified by Kazakov discloses the apparatus of claim 1, wherein the apparatus is a computing device that further includes:
a central processing unit (Uhrenholt’s CPU 1);
a display (Uhrenholt’s display 7); and
network interface circuitry (Uhrenholt’s interconnect 5).
Therefore, it would have been obvious before the effective filing date of the claimed invention to combine Uhrenholt’s to use cache coherency protocol as taught by Kazakov, to save memory resource and reduce overhead.
Claim 13 recites the functions of the apparatus recited in claim 1 as method steps. Accordingly, the mapping of the prior art to the corresponding functions of the apparatus in claim 1 applies to the method steps of claim 13.
Claim 17 recites the functions of the apparatus recited in claim 1 as medium steps. Accordingly, the mapping of the prior art to the corresponding functions of the apparatus in claim 1 applies to the medium steps of claim 17.
Claim 2-3, 14 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Uhrenholt U.S. Patent Application 20220027283 in view of Kazakov U.S. Patent Application 20190066352, and further in view of Wang U.S. Patent Application 20200183890.
Regarding claim 2, Uhrenholt as modified by Kazakov discloses metadata and corresponding blocks of data (Uhrenholt's paragraph [0028]: when a block of data that is stored in the memory in a compressed form is to be loaded into the cache, the compressed block of data having a set of associated compression metadata). However, Uhrenholt as modified by Kazakov fails to disclose providing atomicity for accesses to metadata and corresponding data.
Wang discloses providing atomicity for accesses to metadata and corresponding data (paragraph [0016]: an upgrade lock that enforces atomicity of file stat (metadata) access, even while still permitting multiple processes to concurrently read from and/or write to the file data).
Therefore, it would have been obvious before the effective filing date of the claimed invention to combine Uhrenholt and Kazakov’s to provide atomicity access as taught by Wang, to prevent concurrent attempts to update the metadata.
Regarding claim 3, Uhrenholt as modified by Kazakov and Wang discloses the apparatus of claim 2, wherein the metadata coherence circuitry is configured to determine hits and misses for the cache circuitry based on metadata status (Kazakov’s paragraph [0033]: If the query hits in the metadata cache 330, the metadata cache 330 returns the metadata 330 to the pipeline 355, which uses the metadata 330 to determine the residency status... If the query misses in the metadata cache 330, the query is forwarded to the GPU memory 305).
Therefore, it would have been obvious before the effective filing date of the claimed invention to combine Uhrenholt and Kazakov’s to provide atomicity access as taught by Wang, to prevent concurrent attempts to update the metadata.
Claim 14 recites the functions of the apparatus recited in claim 2 as method steps. Accordingly, the mapping of the prior art to the corresponding functions of the apparatus in claim 2 applies to the method steps of claim 14.
Claim 18 recites the functions of the apparatus recited in claim 2 as medium steps. Accordingly, the mapping of the prior art to the corresponding functions of the apparatus in claim 2 applies to the medium steps of claim 18.
Claim 4, 9, 15 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Uhrenholt U.S. Patent Application 20220027283 in view of Kazakov U.S. Patent Application 20190066352, and further in view of Akenine-Moller U.S. Patent Application 20180089091.
Regarding claim 4, Uhrenholt as modified by Kazakov discloses all the features with respect to claim 1 as outlined above. However, Uhrenholt as modified by Kazakov fails to disclose non-compressed portions of blocks of data; and assign different addresses in a same address space for a compressed block of data and non-compressed portions of the compressed block of data.
Akenine-Moller discloses non-compressed portions of blocks of data; and assign different addresses in a same address space for a compressed block of data and non-compressed portions of the compressed block of data (paragraph [0141]: address 1631B can track a block of data stored in memory and status 1632 can store status such as coherency data (e.g., cache coherency, etc.) while codec 1633B stores an indication of whether the data at address 1631B is compressed or uncompressed, as well as the type or degree of compression that has been used; see fig. 16 different addresses in same address space).
Therefore, it would have been obvious before the effective filing date of the claimed invention to combine Uhrenholt and Kazakov’s to assign address as taught by Akenine-Moller, to provide cache and compression logic for a graphics processor.
Regarding claim 9, Uhrenholt as modified by Kazakov and Akenine-Moller discloses the apparatus of claim 1, wherein the apparatus includes scoreboard circuitry configured to track status of non-compressed portions of data blocks stored in the cache circuitry (Akenine-Molle’s paragraph [0141]: address 1631B can track a block of data stored in memory and status 1632 can store status such as coherency data (e.g., cache coherency, etc.) while codec 1633B stores an indication of whether the data at address 1631B is compressed or uncompressed, as well as the type or degree of compression that has been used; see fig. 16 different addresses in same address space).
Therefore, it would have been obvious before the effective filing date of the claimed invention to combine Uhrenholt and Kazakov’s to assign address as taught by Akenine-Moller, to provide cache and compression logic for a graphics processor.
Claim 15 recites the functions of the apparatus recited in claim 4 as method steps. Accordingly, the mapping of the prior art to the corresponding functions of the apparatus in claim 4 applies to the method steps of claim 15.
Claim 19 recites the functions of the apparatus recited in claim 4 as medium steps. Accordingly, the mapping of the prior art to the corresponding functions of the apparatus in claim 4 applies to the medium steps of claim 19.
Claim 5, 16 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Uhrenholt U.S. Patent Application 20220027283 in view of Kazakov U.S. Patent Application 20190066352, and further in view of Sadowski U.S. Patent Application 20180246657.
Regarding claim 5, Uhrenholt as modified by Kazakov discloses all the features with respect to claim 1 as outlined above. However, Uhrenholt as modified by Kazakov fails to disclose use different hashing techniques to generate address information for compressed writes and non-compressed writes to the same block of graphics data.
Sadowski discloses use different hashing techniques to generate address information for compressed writes and non-compressed writes to the same block of graphics data (paragraph [0037]: At step 510, if the compression indicator indicates that the block is compressed, then the method 500 proceeds to step 510 and if the compression indicator indicates that the block is not compressed, then the method 500 proceeds to step 514. At step 514, the memory interface 306 stores the uncompressed block in the buffer 312 without hashing the block; paragraph [0038]: if the block is indicated as being compressed, then the method 500 proceeds to step 512. At step 512, the hash unit 308 creates a hash of the compressed block).
Therefore, it would have been obvious before the effective filing date of the claimed invention to combine Uhrenholt and Kazakov’s to use hash as taught by Sadowski, to prevent data collision.
Claim 16 recites the functions of the apparatus recited in claim 5 as method steps. Accordingly, the mapping of the prior art to the corresponding functions of the apparatus in claim 5 applies to the method steps of claim 16.
Claim 20 recites the functions of the apparatus recited in claim 5 as medium steps. Accordingly, the mapping of the prior art to the corresponding functions of the apparatus in claim 5 applies to the medium steps of claim 20.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Uhrenholt U.S. Patent Application 20220027283 in view of Kazakov U.S. Patent Application 20190066352, and further in view of Smith U.S. Patent Application 20170371660.
Regarding claim 10, Uhrenholt as modified by Kazakov discloses writes for buffer writes and compressed pixel writes to a given address (Uhrenholt’s paragraph [0247]: the data encoder 22 encodes (compresses) the uncompressed data for the block that it has read from the L2 cache (step 125), and then writes the compressed data (the compressed cache lines) back to the memory 6 (step 126); paragraph [0250]: the data encoder simply operates to write the uncompressed lines for the block read from the L2 cache back to the memory system 6 (step 131)). However, Uhrenholt as modified by Kazakov fails to disclose providing write-after-write ordering.
Smith discloses providing write-after-write ordering (paragraph [0188]: the committed store instruction that is earliest in program order can be written to the memory hierarchy before store instructions that are later in program order. By following this order, write-after-write dependencies can be satisfied).
Therefore, it would have been obvious before the effective filing date of the claimed invention to combine Uhrenholt and Kazakov’s to provide write-after-write as taught by Smith, to improve processor performance.
Allowable Subject Matter
Claim 6 and 11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 6 is about the shader processor circuitry is configured to write a second compressed block of data to a memory circuit of the apparatus without caching the second compressed block of data in the cache circuitry; and the metadata coherence circuitry is configured to invalidate cached metadata for the second compressed block of data in response to the write.
Uhrenholt 20220027283, Kazakov 20190066352 and Koker 20220114108 combined cannot teach these features perfectly. These limitations when read in light of the rest of the limitations in the claim and the claims to which it depends make the claim allowable subject matter.
Claim 11 is about the shader processor circuitry is configured to:
execute a graphics application that aliases heap data structures in time using at least partially overlapping addresses, wherein to execute the graphics application, the apparatus is configured to: compress at least a portion of data stored in a first aliased heap structure; not compress data stored in a second aliased heap structure.
Uhrenholt 20220027283, Kazakov 20190066352 and Smith 20170371660 combined cannot teach these features perfectly. These limitations when read in light of the rest of the limitations in the claim and the claims to which it depends make the claim allowable subject matter.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Yi Yang whose telephone number is (571)272-9589. The examiner can normally be reached on Monday-Friday 9:00 AM-6:00 PM EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Daniel Hajnik can be reached on 571-272-7642. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
/YI YANG/
Primary Examiner, Art Unit 2616