Prosecution Insights
Last updated: October 26, 2026
Application No. 18/795,643

SEMICONDUCTOR MEMORY DEVICE

Non-Final OA §102§103
Filed
Aug 06, 2024
Priority
Nov 29, 2023 — RE 10-2023-0169366
Examiner
REIDA, MOLLY KAY
Art Unit
Tech Center
Assignee
Samsung Electronics Co., Ltd.
OA Round
1 (Non-Final)
82%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
86%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allowance Rate
367 granted / 445 resolved
+22.5% vs TC avg
Minimal +3% lift
Without
With
+3.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
16 currently pending
Career history
476
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
50.2%
+10.2% vs TC avg
§102
30.0%
-10.0% vs TC avg
§112
17.6%
-22.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 445 resolved cases

Office Action

§102 §103
DETAILED ACTION Priority Acknowledgment is made of applicant's claim for foreign priority based on an application filed in Korea on 11/29/2023. It is noted, however, that applicant has not filed a certified copy of the KR10-2023-0169366 application as required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statement (IDS) submitted on 08/06/2024 has been considered by the examiner. Drawings The drawings are objected to because Figure 29 shows what is supposed to be etch stop film 870 (para. 000154-000155) pointing to the capacitor dielectric film instead of the etch stop film. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 2, 7, 9, and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Son et al. (US pub. 2021/0257371). Regarding independent claim 1, Son teaches a semiconductor memory device (Fig. 25; para. 0085+) comprising: a substrate (100) including active regions (ACT); bitline structures (BLS) extending in a direction on the active regions; landing pads (115) electrically connected to the active regions, on the bitline structures; interlayer insulating films (102) between the landing pads, on the bitline structures; capacitor structures (CAS) including lower electrodes (BE) that are on the landing pads, dielectric films (140) that extend along the lower electrodes, and an upper electrode (TE) that is on the dielectric films; and etch stop films (120) between the interlayer insulating films and the capacitor structures, wherein the upper electrode includes a first portion (portion below the bottom bulge of BE) that is on the etch stop films, and a second portion (portion adjacent to the bulge portion of BE) that is on the first portion, and wherein a width of the second portion is less than a width of the first portion (Fig. 25). Re claim 2, Son teaches wherein the lower electrodes include first lower electrodes (porition of BE below the bottom bulge portion) that contact the landing pads, third lower electrodes (portion adjacent to 130L) that are on the first lower electrodes, and second lower electrodes (bottom bulge portion) that are between the first lower electrodes and the third lower electrodes. Re claim 7, Son teaches wherein a width of the second lower electrodes is tapered toward the third lower electrodes (Fig. 25). Re claim 9, Son teaches wherein the capacitor structures further include a plurality of electrode support layers (130L and/or 130U) that support the lower electrodes. Re claim 10, Son teaches wherein the landing pads and the lower electrodes include a material comprising at least one of silicon (Si), nickel (Ni), titanium (Ti), tungsten (W), molybdenum (Mo), zirconium (Zr), niobium (Nb), or tantalum (Ta), or a nitride of the material, or an oxide of the material, or the nitride of the material and the oxide of the material (para. 0025, 0033). Claim(s) 12, 13, and 15-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US Pub. 2023/0200053). Regarding independent claim 12, Kim teaches a semiconductor memory device (Figs. 2, 3A-3D; para. 0021+) comprising: a substrate (110) including active regions (118) that are defined by device isolation films (116) (para. 0028); wordline structures (120) extending in a first direction (X) on the active regions (para. 0028); bitline structures (140) extending in a second direction (Y) that intersects the first direction, on the wordline structures (para. 0028); buried contacts (170) electrically connected to the active regions, between the bitline structures (para. 0048); landing pads (190) electrically connected to the active regions, on the bitline structures (para. 0052); interlayer insulating films (195) between the landing pads, on the bitline structures(0054); capacitor structures (200) including lower electrodes (210) that are on the landing pads, dielectric films (230) that extend along the lower electrodes, and an upper electrode (230) that is on the dielectric films (para. 0028); and etch stop films (300) between the interlayer insulating films and the capacitor structures (para. 0055), wherein the lower electrodes include first lower electrodes (portion below top of 320) that contact the landing pads, third lower electrodes (portion above bottom of 330) that are on the first lower electrodes, and second lower electrodes (portion between top of 320 and bottom of 330) that are between the first lower electrodes and the third lower electrodes (Fig. 3A), and wherein the first lower electrodes, the second lower electrodes, and the third lower electrodes form an “I” shape together (Fig. 3A; refer also to Fig. 8J). Re claim 13, Kim teaches wherein a width of the second lower electrodes is less than a width of the first lower electrodes and a width of the third lower electrodes (Fig. 3A; refer also to Fig. 8J). Re claim 15, Kim teaches a barrier film between the buried contacts and the landing pads (para. 0052). Re claim 16, Kim teaches wherein in a third direction that is perpendicular to the first and second directions, sidewalls of the first lower electrodes are collinear with sidewalls of the landing pads (Fig. 3A). Re claim 17, Kim teaches wherein in a third direction that is perpendicular to the first and second directions, sidewalls of the etch stop films are collinear with sidewalls of the interlayer insulating films (Fig. 3A). Re claim 18, Kim teaches wherein the first lower electrodes and the second lower electrodes include the same material (Fig. 3A; refer also to para. 0111). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 8 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Son et al. (US pub. 2021/0257371) in view of Kim et al. (US Pub. 2023/0200053). Re claim 8, Son is silent with respect to a barrier film between the bitline structures and the landing pads. Kim teaches wherein the landing pad may be formed on a barrier film (para. 0054). It would have been obvious to one of ordinary skill in the art at the time of filing to include a barrier layer within the device of Son as taught by Kim such that barrier film between the bitline structures and the landing pads as claimed for the purpose of preventing diffusion of the landing pad material into the surrounding insulating layers. Re claim 11, Son teaches wherein the etch stop film includes; for example, at least one selected from oxide, nitride, and oxynitride (para. 0026) but is silent with respect to silicon boron nitride (SiBN) explicitly. Kim teaches wherein the etch stop films include silicon boron nitride (SiBN) (para. 0055); therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to choose silicon boron nitride (SiBN) as the etch stop of film of Son with a reasonable expectation of success because the claimed material is known to be used as an etch stop film. It is considered obvious to select a known material based on its suitability for an intended purpose (MPEP 2144.07). Allowable Subject Matter Claims 19 and 20 are allowed. The following is a statement of reasons for the indication of allowable subject matter: there is no teaching, suggestion, or motivation from the prior art of record, nor does the prior art of record otherwise make obvious the limitations of “wherein a width of the second lower electrodes is less than a width of the first lower electrodes, and wherein a width of the second portion of the upper electrode structure is less than a width of the first portion of the upper electrode structure”, in combination with the other limitations. Claims 3-6 and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOLLY KAY REIDA whose telephone number is (571)272-4237. The examiner can normally be reached M-F 8:30-5:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached at (408)918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MOLLY K REIDA/Examiner, Art Unit 2899
Read full office action

Prosecution Timeline

Aug 06, 2024
Application Filed
Oct 08, 2026
Non-Final Rejection mailed — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12690321
DISPLAY DEVICE AND MANUFACTURING METHOD OF THE SAME
3y 9m to grant Granted Jul 21, 2026
Patent 12684823
LAYER STRUCTURES INCLUDING CONFIGURATION INCREASING OPERATION CHARACTERISTICS, METHODS OF MANUFACTURING THE SAME, ELECTRONIC DEVICES INCLUDING LAYER STRUCTURES, AND ELECTRONIC APPARATUSES INCLUDING ELECTRONIC DEVICES
4y 1m to grant Granted Jul 14, 2026
Patent 12672279
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
3y 4m to grant Granted Jun 30, 2026
Patent 12666590
SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME
3y 6m to grant Granted Jun 23, 2026
Patent 12660161
CAPACITOR STRUCTURE AND METHOD FOR MANUFACTURING SAME, SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING SAME
3y 1m to grant Granted Jun 16, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
82%
Grant Probability
86%
With Interview (+3.2%)
2y 2m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 445 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month