DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in Korea on 2/20/24. It is noted, however, that applicant has not filed a certified copy of the 10-2024-0024159 application as required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 8/6/24 & 6/9/25 are being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shirakura et al. (US 2021/0294504).
With respect to claim 1,
Figure 1 of Shirakura discloses a storage device comprising:
a non-volatile memory device (30);
a memory controller (20) configured to control input of first data to the non-volatile memory device and output of second data from the non-volatile memory device (see double arrows on either end of 20); and
a device interconnect layer (see Figure 1) configured to transmit signals received from a host (2) to the memory controller (20),
wherein the device interconnect layer comprises
a first pad (22) configured to input the first data to be stored in the non-volatile memory device (30) and to output the second data from the non-volatile memory device (30),
a second pad (10) configured to receive a link startup mode signal from the host (2), the link startup mode signal indicating a link startup mode of the memory controller,
a pull-down resistor (within 212 – see R22 of Figure 5) between the second pad (10) and a ground terminal (Vss), and
a pad level control circuit (24) configured to control a voltage level of the second pad by controlling connection or disconnection of the pull-down resistor to the ground terminal based on the link startup mode signal (Paragraph 42).
With respect to claim 12,
Figure 1 of Shirakura discloses a universal flash storage (UFS) device comprising:
a flash memory (30 – Paragraph 23);
a UFS device controller (20) configured to control input of first data to the flash memory and output of second data from the flash memory (see double arrows on either end of 20); and
a UFS device interface (see Figure 1) configured to transmit signals received from a UFS host (2) to the UFS device controller (20),
wherein the UFS device interface comprises
a first pad (22) configured to input the first data to be stored in the flash memory (30) and to output the second data from the flash memory (30),
a second pad (10) configured to receive a link startup mode signal from the UFS host (2), the link startup mode signal indicating a link startup mode of the UFS device controller,
a pull-down resistor (within 212 – see R22 of Figure 5) configured to determine a voltage level of the second pad, and
a pad level control circuit (24) configured to control the voltage level of the second pad by controlling connection or disconnection of the pull-down resistor to a ground terminal based on the link startup mode signal (Paragraph 42).
Allowable Subject Matter
Claims 2-11 and 13-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 17-20 appear to comprise allowable subject matter.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jany Richardson whose telephone number is (571)270-5074. The examiner can normally be reached Monday - Friday, 7:00am to 3:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander Taningco can be reached at 571-272-8048. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JANY RICHARDSON/ Primary Examiner, Art Unit 2844
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