Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-13 and 21-27 are pending.
Response to Arguments
The specification objections have been withdrawn in view of the entered amendments.
Applicant's arguments with respect to the previously applied 35 USC 102 have been considered but are moot in view of the new ground(s) of rejection.
Applicant's arguments with respect to the previously applied references in view of the amended claims have been considered but are not persuasive.
Specifically, the applicant argues with respect to claim 1 that Kekicheff does not teach the first security module retrieving the processor module identifier and the random number from the processor module, computing the second authentication key based on the processor module identifier and the random number retrieved from the processor module, and determining whether to allow the initialization of the processor module based on the first authentication key and the second authentication key.
The examiner disagrees and notes it is the combination of Paulraj and Kekicheff that disclose claim 1. However, with regard to the language of claim 1 and Kekicheff, Kekicheff discloses a controller to:
retrieve, from the processor module, information comprising a processor module identifier of the processor module and a random number stored at the processor module, the information comprising the processor module identifier and the random number set by a second security module ([0038]-[0040], particularly, “Predetermined device data is read by the registration code 110 at block 606. Because the registration code 110 or the registration application 112 is device-specific, the device-specific data read can be tailored based on type. That is, different data is used when registering a smart phone vs. Ea fitness tracker, or even fitness trackers from different manufacturers. In an embodiment, a model number, serial number, and operating system version can be used as the device-specific data. In one embodiment, 60 bytes of device-specific data can be used. In some cases, the device-specific data is data from transient memory or a version number of a tool, such as a Java API…At block 608, a pseudo-random (or random) number 117 may be obtained.”); and
compute an authentication key based on the information comprising the processor module identifier and the random number retrieved from the processor module ([0039]-[0041], particularly, “The device-data and pseudo-random number are combined at block 610 to develop a base number…. At block 612, the secure identifier is generated from the base number, that is the combination of the device-specific data and the pseudo-random number 117.”)
Paulraj is the primary reference and relied upon to disclose the rest of claim 1, see below rejection, particularly the argued “determining” limitation.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-13 and 21-27 are rejected under 35 U.S.C. 103 as being unpatentable over Paulraj et al (US Pub. No. 2024/0303339), hereafter, “Paulraj,” in view of Kekicheff et al (US Pub. No. 2019/0334888), hereafter, “Kekicheff.”
As to claim 1, Paulraj discloses a first security module (Fig. 1 and Abstract) comprising:
a connector interface to removably connect to a processor module ([0027], particularly, “Unlike existing servers, where the BMC is integrated on a processor motherboard and cannot be easily moved to another system, DC-SCM 206 is pluggable and can be moved to a new server and new HPM 201 relatively easily.”); and
a controller ([0026], particularly, “DC-SCM 206 includes an iDRAC 208 or other remote access controller or baseboard management controller (BMC). iDRAC 208 includes RoT Binding daemon 209, such as a background software application or process running on iDRAC 208. DC-SCM 206 also includes a security processor 210 stores credentials, licenses, security certificates, and configuration hash values for use in establishing bindings or trust between system components.”) to:
retrieve, from the processor module, information stored at the processor module, the information set by a second security module ([0033], particularly, “When the factory mode is active, iDRAC 208 retrieves hardware identity certificates from all of the SPDM-capable hardware devices present in HPM 201, such as CPU 202, memory devices 203, 204, and smart device 205. The hardware identity certificates may be obtained using the SPDM Get_Certificate request message sent by iDRAC 208, which causes the hardware devices to respond with an SPDM Certificate response message.” See also, [0044]-[0045], particularly, “In step 306, iDRAC 31 calculates an overall hash value for all of the hardware identity certificates and firmware measurements for CPU 33 and memory 34 and stores the hash value either locally or with security processor 35 This binds HPM 32 to the DC-SCM associated with iDRAC 31 and sets the system mode to HPM-to-DC-SCM BOUND mode and ends the factory mode.”);
read a first authentication key from a memory of the first security module ([0044]-[0046], particularly, “After the system is installed at a customer site, such as a data center, steps 307-312 may be performed. In steps 307 and 308, power on messages are sent to security processor 35 and iDRAC 31. As part of the boot process, iDRAC 31 obtains hardware identity certificates and firmware measurements from hardware devices 33, 34 present on HPM 32.”);
compute a second authentication key based on the information retrieved from the processor module ([0045]-[0046], particularly, “iDRAC 208 recalculates the overall hash value and fetches the stored hash value in step 309 from security processor 34. In step 310, iDRAC 31 determines whether both hash values match (i.e., factory hash value and recent power on hash value) and then validates the binding between the DC-SCM associated with iDRAC 31 and HPM 32.”); and
determine whether to allow an initialization of the processor module based on the first authentication key and the second authentication key ([0045]-[0046], particularly, “In step 310, iDRAC 31 determines whether both hash values match (i.e., factory hash value and recent power on hash value) and then validates the binding between the DC-SCM associated with iDRAC 31 and HPM 32. In step 311, if the binding is valid, then iDRAC 31 initiates power on for the HPM 32 components and allows the CPU 33 to boot.”)
However, Paulraj does not explicitly disclose the information retrieved from processor module comprising the processor module identifier and the random number and therefore
the second authentication key based on the information comprising the processor module identifier and the random number retrieved from the processor module.
But, Kekicheff discloses retrieve, from the processor module, information comprising a processor module identifier of the processor module and a random number stored at the processor module, the information comprising the processor module identifier and the random number set by a second security module ([0038]-[0040], particularly, “Predetermined device data is read by the registration code 110 at block 606. Because the registration code 110 or the registration application 112 is device-specific, the device-specific data read can be tailored based on type. That is, different data is used when registering a smart phone vs. Ea fitness tracker, or even fitness trackers from different manufacturers. In an embodiment, a model number, serial number, and operating system version can be used as the device-specific data. In one embodiment, 60 bytes of device-specific data can be used. In some cases, the device-specific data is data from transient memory or a version number of a tool, such as a Java API…At block 608, a pseudo-random (or random) number 117 may be obtained.”); and
compute an authentication key based on the information comprising the processor module identifier and the random number retrieved from the processor module ([0039]-[0041], particularly, “The device-data and pseudo-random number are combined at block 610 to develop a base number…. At block 612, the secure identifier is generated from the base number, that is the combination of the device-specific data and the pseudo-random number 117.”)
Therefore it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the application to combine the teachings of Paulraj and Kekicheff in order to provide a reliable means to generate unique identifiers for devices to be used in later applications.
As to claims 22 and 26, they are rejected by a similar rationale by that set forth in claim 1’s rejection.
As to claim 2, the teachings of Paulraj and Kekicheff as combined for the same reasons set forth in claim 1’s rejection further disclose the first security module is different from or the same as the second security module (Paulraj, [0044]-[0046]).
As to claim 3, the teachings of Paulraj and Kekicheff as combined for the same reasons set forth in claim 1’s rejection further disclose the controller is to prevent the initialization of the processor module based on the controller determining that the second authentication key is different from the first authentication key (Paulraj, [0045]-[0046], particularly, “In step 310, iDRAC 31 determines whether both hash values match (i.e., factory hash value and recent power on hash value) and then validates the binding between the DC-SCM associated with iDRAC 31 and HPM 32. In step 311, if the binding is valid, then iDRAC 31 initiates power on for the HPM 32 components and allows the CPU 33 to boot.”).
As to claim 4, the teachings of Paulraj and Kekicheff as combined for the same reasons set forth in claim 1’s rejection further disclose a mismatch of the second authentication key and the first authentication key indicates that the first security module is different from the second security module (Paulraj, [0045]-[0046], particularly, “In step 310, iDRAC 31 determines whether both hash values match (i.e., factory hash value and recent power on hash value) and then validates the binding between the DC-SCM associated with iDRAC 31 and HPM 32. In step 311, if the binding is valid, then iDRAC 31 initiates power on for the HPM 32 components and allows the CPU 33 to boot.”).
As to claim 5, the teachings of Paulraj and Kekicheff as combined for the same reasons set forth in claim 1’s rejection further disclose the first authentication key was generated by the first security module when binding with a processor module (Paulraj, [0044]-[0046]).
As to claim 6, the teachings of Paulraj and Kekicheff as combined for the same reasons set forth in claim 1’s rejection further disclose the controller is to: retrieve a certificate from the processor module; and determine whether the certificate is valid based on a digital signature in the certificate, wherein the reading of the first authentication key, the computing of the second authentication key, and the determining of whether to allow the initialization are performed in response to determining that the certificate is valid (Paulraj, [0044]-[0046], particularly, “In step 310, iDRAC 31 determines whether both hash values match (i.e., factory hash value and recent power on hash value) and then validates the binding between the DC-SCM associated with iDRAC 31 and HPM 32. In step 311, if the binding is valid, then iDRAC 31 initiates power on for the HPM 32 components and allows the CPU 33 to boot.”).
As to claim 7, the teachings of Paulraj and Kekicheff as combined for the same reasons set forth in claim 1’s rejection disclose the processor module identifier comprises: a serial number from the processor module, and the second authentication key is based on the random number and the serial number (Kekicheff, Abstract and [0038], particularly, “In an embodiment, a model number, serial number, and operating system version can be used as the device-specific data.”)
As to claim 8, the teachings of Paulraj and Kekicheff as combined for the same reasons set forth in claim 1’s rejection disclose the serial number is set while the processor module is in a factory mode (Paulraj, [0033] and Kekicheff, [0037]-[0038]).
As to claim 9, the teachings of Paulraj and Kekicheff as combined for the same reasons set forth in claim 1’s rejection disclose the serial number is set by the second security module (Paulraj, [0033] and Kekicheff, [0037]-[0038]).
As to claim 10, the teachings of Paulraj and Kekicheff as combined for the same reasons set forth in claim 1’s rejection disclose after the setting of the serial number the processor module is transitioned from the factory mode to a production mode, wherein the information is retrieved by the first security module from the processor module in the production mode (Paulraj, [0033] and Kekicheff, [0037]-[0038]).
As to claim 11, the teachings of Paulraj and Kekicheff as combined for the same reasons set forth in claim 1’s rejection further disclose the controller is to: request, from the processor module, a pairing value generated by the second security module based on first information of the processor module and second information of the second security module, wherein the request comprises a controller- provided authentication key sent from the controller to the processor module, the controller-provided authentication key comprising the first authentication key or the second authentication key; and receive, at the controller, the pairing value from the processor module in response to the request, wherein the receipt of the pairing value indicates a validity of the controller- provided authentication key (Paulraj, [0044]-[0046]).
As to claim 12, the teachings of Paulraj and Kekicheff as combined for the same reasons set forth in claim 1’s rejection further disclose first information comprises processor module identifier, and second information identifier comprises and an identifier a second security module (Kekicheff, Abstract and [0038]-[0041], particularly, “In an embodiment, a model number, serial number, and operating system version can be used as the device-specific data.”)
As to claim 13, the teachings of Paulraj and Kekicheff as combined for the same reasons set forth in claim 1’s rejection further disclose the pairing value comprises a hash value derived from applying a hash function on the first information and the second information (Paulraj, [0044]-[0046]).
As to claims 21, 23, and 27, the teachings of Paulraj and Kekicheff as combined for the same reasons set forth in claim 1’s rejection further disclose the random number was set by the second security module and stored in the processor module when binding the second security module with the processor module (Kekicheff, [0039]-[0041], particularly, “The device-data and pseudo-random number are combined at block 610 to develop a base number…. At block 612, the secure identifier is generated from the base number, that is the combination of the device-specific data and the pseudo-random number 117.”)
As to claim 24, the teachings of Paulraj and Kekicheff as combined for the same reasons set forth in claim 1’s rejection further disclose the instructions upon execution cause the first security module to: prevent the initialization of the processor module based on detecting a mismatch between the second authentication key and the first authentication key, wherein the mismatch of the second authentication key and the first authentication key indicates that the first security module is different from the second security module (Paulraj, [0043]-[0046]).
As to claim 25, the teachings of Paulraj and Kekicheff as combined for the same reasons set forth in claim 1’s rejection further disclose he instructions upon execution cause the first security module to: retrieve a certificate from the processor module; and determine whether the certificate is valid based on a digital signature in the certificate, wherein the reading of the first authentication key, the computing of the second authentication key, and the determining of whether to allow the initialization are performed in response to determining that the certificate is valid (Paulraj, [0043]-[0046]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THOMAS J DAILEY whose telephone number is (571)270-1246. The examiner can normally be reached on 9:30am-6:00pm.
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/THOMAS J DAILEY/ Primary Examiner, Art Unit 2458
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