Prosecution Insights
Last updated: October 02, 2026
Application No. 18/795,885

PHASED-ARRAY TRANSMITTER BASED ON INTERMEDIATE-FREQUENCY LOCAL-OSCILLATOR (IFLO) PHASE-SHIFTING ARCHITECTURE

Non-Final OA §103
Filed
Aug 06, 2024
Priority
Aug 11, 2023 — provisional 63/518,882
Examiner
YUN, EUGENE
Art Unit
Tech Center
Assignee
The Hong Kong University of Science and Technology
OA Round
1 (Non-Final)
85%
Grant Probability
Favorable
1-2
OA Rounds
3m
Est. Remaining
90%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
865 granted / 1013 resolved
+25.4% vs TC avg
Minimal +4% lift
Without
With
+4.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
28 currently pending
Career history
1044
Total Applications
across all art units

Statute-Specific Performance

§101
3.4%
-36.6% vs TC avg
§103
48.3%
+8.3% vs TC avg
§102
26.4%
-13.6% vs TC avg
§112
2.4%
-37.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1013 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-4, 22, and 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 8,618,983) in view of McCune, Jr. (US 9,041,602). Referring to Claim 1, Chen teaches a phased-array transmitter system, comprising: a signal path comprising: a phase-shifter configured to generate a phase-shifted signal (see phase shifter 111 in fig. 1); a first mixer configured to mix the phase-shifted signal with a baseband signal to generate a first mixed signal (see mixer 109 in fig. 1 which mixes the phase shifter signal from 111 and the baseband signal from 108); a variable gain amplifier (VGA) configured to perform phase-invariant gain- controlled amplification on the first mixed signal (see VGA 110 which receives the output from mixer 109 in fig. 1); a second mixer configured to mix the amplified first mixed signal with another signal to generate a radiofrequency (RF) signal (see mixer 112 which mixes signal from 105 and from VGA 110 in fig. 1); and a power amplifier configured to amplify the RF signal and feed the amplified RF signal to an antenna (see PA 128 in fig. 1 whose output leads to antenna 130-1). McCune teaches a plurality of signal paths (see multiple signal paths in fig. 14) comprising a mixer configured to mix an amplified signal with an RFLO signal to generate a radiofrequency (RF) signal (see mixer 1410 mixing an amplified signal 1408 and an RFLO signal from RF OSCILLATOR in fig. 14 where a skilled artisan would be able to apply the mixer of McCune to the device of Chen since the output of the mixer of McCune also leads to a PA and antenna). Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to provide the teachings of McCune to the device of Chen in order to more efficiently process signals when using a phased array. Referring to Claim 22, Chen teaches phased-array transmitter system, comprising: a phase-shifter configured to generate a phase-shifted signal (see phase shifter 111 in fig. 1); a first mixer configured to mix the phase-shifted signal with a baseband signal to generate a first mixed signal (see mixer 109 in fig. 1 which mixes the phase shifter signal from 111 and the baseband signal from 108); a variable gain amplifier (VGA) configured to perform phase-invariant gain- controlled amplification on the first mixed signal (see VGA 110 which receives the output from mixer 109 in fig. 1); a second mixer configured to mix the amplified first mixed signal with another signal to generate a radiofrequency (RF) signal (see mixer 112 which mixes signal from 105 and from VGA 110 in fig. 1); and a power amplifier configured to amplify the RF signal and feed the amplified RF signal to an antenna (see PA 128 in fig. 1 whose output leads to antenna 130-1). McCune teaches a mixer configured to mix an amplified signal with an RFLO signal to generate a radiofrequency (RF) signal (see mixer 1410 mixing an amplified signal 1408 and an RFLO signal from RF OSCILLATOR in fig. 14 where a skilled artisan would be able to apply the mixer of McCune to the device of Chen since the output of the mixer of McCune also leads to a PA and antenna). Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to provide the teachings of McCune to the device of Chen in order to more efficiently process signals when using a phased array. Referring to Claim 23, Chen teaches a method for operating a phased-array transmitter system, comprising: producing, by a phase-locked loop, an output frequency (see col. 4, line 59 to col. 5, line 15 which shows a PLL producing a frequency); dividing the output frequency to produce multi-phase signals (see col. 4, line 59 to col. 5, line 15 which shows a frequency produced by the PLL being divided); and phase-shifting a respective signal (see phase shifter 111 in fig. 1); mixing the respective signal with a baseband signal (see mixer 109 in fig. 1 which mixes the phase shifter signal from 111 and the baseband signal from 108); amplifying the mixed signal (see VGA 110 which receives the output from mixer 109 in fig. 1); mixing the amplified mixed signal with another signal to generate a radiofrequency (RF) signal (see mixer 112 which mixes signal from 105 and from VGA 110 in fig. 1); amplifying the RF signal; and sending the RF signal to an antenna (see PA 128 in fig. 1 whose output leads to antenna 130-1). McCune teaches a plurality of signal paths (see multiple signal paths in fig. 14) comprising a mixer configured to mix an amplified signal with an RFLO signal to generate a radiofrequency (RF) signal (see mixer 1410 mixing an amplified signal 1408 and an RFLO signal from RF OSCILLATOR in fig. 14 where a skilled artisan would be able to apply the mixer of McCune to the device of Chen since the output of the mixer of McCune also leads to a PA and antenna). Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to provide the teachings of McCune to the device of Chen in order to more efficiently process signals when using a phased array. Referring to Claim 2, Chen also teaches the signal path including an 8-2 phase multiplexer (see fig. 2 which shows a dual 8 channel multiplexer). McCune teaches four signal paths (see 4 signal paths in fig. 1). Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to provide the teachings of McCune to the device of Chen in order to more efficiently process signals when using a phased array. Referring to Claim 3, Chen also teaches a divide-by-4 (Div-4) circuit configured to produce 8-phase intermediate frequency local oscillator (IFLO) signals (see fig. 2 which shows signals divided into 4 at 206 and then divided into 8 at 204 and col. 6, line 61 to col. 7, line 12 which shows the signals as IFLO signals). Referring to Claim 4, McCune also teaches wherein the phase-shifter of each of the four signal paths takes as input a pair of the 8-phase IFLO signals produced by the Div-4 circuit (see fig. 6 which shows the pairs of signals input to phase shifters 602). Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen and McCune and further in view of Denney et al. (US 5,995,062). Referring to Claim 17, the combination of Chen and McCune does not teach the phase-shifter of each of the four signal paths comprising a phase multiplexer and an intermedia frequency local oscillator (IFLO) phase-interpolation-based phase-shifter. Denney teaches the phase-shifter of each of the four signal paths comprising a phase multiplexer and an intermedia frequency local oscillator (IFLO) phase-interpolation-based phase-shifter (see col. 6, lines 14-35 which shows signals in each signal path phase shifted 72 using IFLO 76 interpolation). Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to provide the teachings of Denney to the modified device of Chen and McCune in order to better maintain optimum antenna coverage during communication. Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen and McCune and further in view of Cevrero (US 2019/0081600). Referring to Claim 18, the combination of Chen and McCune does not teach the VGA of each of the four signal paths as a transadmittance-transimpedance (TAS-TIS) VGA. Cervero teaches the VGA of each of the four signal paths as a transadmittance-transimpedance (TAS-TIS) VGA (see fig. 3 which shows the VGA as a TAS-TIS amplifier 200 noting that a skilled artisan would be able to implement the TAS-TIS amplifier to replace the VGA of Chen without impacting the operability of the device). Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to provide the teachings of Cervero to the modified device of Chen and McCune in order to better regulate power of the device. Allowable Subject Matter Claims 5-16 and 19-21 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Regarding Claim 5, Chen, McCune, Denney, and Cervero do not teach the 8-phase IFLO signals are equally-spaced apart at a spacing of 45 degrees between neighboring signals. Regarding Claim 11, Chen, McCune, Denney, and Cervero do not teach an inductor-less RFLO buffer; and a phase-locked loop configured to provide a first RFLO signal to the Div-4 circuit and to provide a second RFLO signal to the RFLO buffer; wherein the RFLO buffer is configured to provide the RFLO signal to the second mixer of each of the four signal paths. Regarding Claim 19, Chen, McCune, Denney, and Cervero do not teach the TAS-TIS VGA comprises a Q-VGA-transadmittance stage, an I-VGA-transadmittance stage, and a transimpedance stage. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to EUGENE YUN whose telephone number is (571)272-7860. The examiner can normally be reached 9am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wesley Kim can be reached at 5712727867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /EUGENE YUN/ Primary Examiner, Art Unit 2648
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Prosecution Timeline

Aug 06, 2024
Application Filed
Sep 17, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
85%
Grant Probability
90%
With Interview (+4.4%)
2y 5m (~3m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1013 resolved cases by this examiner. Grant probability derived from career allowance rate.

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