DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, claims 2-13 in the reply filed on 2/16/2026 is acknowledged.
Claims 14-21 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 2-6 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Sharma et al (US Pat. 6,799,287; hereinafter referred to as Sharma).
As per claim 2: Sharma teaches a memory device, comprising:
one or more memory arrays (Fig. 1a); and
processing circuitry coupled with the one or more memory arrays (processing circuitry is inherent for memory to operate) and configured to cause the memory device to:
receive a read command associated with a set of data (col. 3, lines 45-52); and
transmit, based at least in part on receiving the read command, a first set of error control bits indicating a failure of a syndrome check operation (Fig. 1b, r syndrome bits), the syndrome check operation comparing (Fig. 1b, 22) a second set of error control bits generated after the set of data is retrieved (col. 3, lines 48-51) and a third set of error control bits stored for the set of data (col. 3, lines 45-48).
As per claim 3: Sharma teaches the memory device of claim 2, wherein the processing circuitry is further configured to cause the memory device to: write the set of data to the one or more memory arrays (col. 3, lines 47-48); generate, based at least in part on writing the set of data to the one or more memory arrays, the third set of error control bits (col. 3, lines 58-60); and store the third set of error control bits in the one or more memory arrays based at least in part on generating the third set of error control bits (col. 3, lines 47-48), wherein receiving the read command occurs after storing the third set of error control bits (col. 3, lines 44-56; data and ECC are necessarily stored before a read can commence on the location).
As per claim 4:
Sharma further teaches the memory device of claim 2, wherein the processing circuitry is further configured to cause the memory device to: retrieve the set of data from the one or more memory arrays based at least in part on receiving the read command (col. 3, lines 45-52); and generate, during an error control operation for the set of data, the second set of error control bits for the set of data based at least in part on retrieving the set of data (col. 3, lines 48-51), wherein transmitting the first set of error control bits is based at least in part on generating the second set of error control bits (Fig. 1b, output of 22 is dependent on input from the second set of error control bits 21).
As per claim 5: Sharma further teaches the memory device of claim 2, wherein, to perform the syndrome check operation, the processing circuitry is configured to cause the memory device to: compare the second set of error control bits with the third set of error control bits (Fig. 1b, 22); determine whether the second set of error control bits is different than the third set of error control bits (col. 3, lines 54-56); and identify a failure of the syndrome check operation based at least in part on determining that the second set of error control bits is different than the third set of error control bits (col. 3, lines 54-56).
As per claim 6: Sharma further teaches the memory device of claim 2, wherein the processing circuitry is further configured to cause the memory device to: generate the first set of error control bits based at least in part on identifying the failure of the syndrome check operation, wherein transmitting the first set of error control bits is based at least in part on generating the first set of error control bits (col. 3, lines 54-56).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over
Sharma in view of Hauck et al (US Pat. 5,878,061; hereinafter referred to as Hauck) in view of Dapper et al (US Pat. Pub. 2002/0102937; hereinafter referred to as Dapper).
As per claim 7: Sharma teaches the memory device of claim 2. Not explicitly disclosed is wherein the processing circuitry is further configured to cause the memory device to: generate, based at least in part on a combination of the set of data and the first set of error control bits, a parity bit that indicates an even state or an odd state; and invert the parity bit based at least in part on identifying the failure of the syndrome check operation, wherein transmitting the first set of error control bits is based at least in part on the parity bit being inverted. However, Hauck in an analogous art teaches a double error syndrome encoding scheme (col. 4, lines 48-60), in which an even state parity indicates a double error (col. 5, lines 4-5).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to utilize a parity bit for indicating odd or even parity of the syndrome as taught by Hauck. This modification would have been obvious for one of ordinary skill in the art at the time of filing because it would have been useful in indication of a double error.
Also not explicitly disclosed is inverting the parity bit based at least in part on identifying the failure of the syndrome check operation. However, Dapper in an analogous art teaches inverting a parity bit to indicate errors in a data (paragraph 214). Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to invert the parity bit of Hauck. This modification would have been obvious for one of ordinary skill in the art at the time of filing because it could have been used to indicate data errors, as taught by Dapper.
Claim(s) 8 are rejected under 35 U.S.C. 103 as being unpatentable over Sharma in view of Meaney et al (US Pat. Pub. 2004/0139374; hereinafter referred to as Meaney).
As per claim 8:
Sharma teaches the memory device of claim 2. Not explicitly disclosed is wherein the processing circuitry is further configured to cause the memory device to: generate a second set of data based at least in part on identifying the failure of the syndrome check operation, each bit of the second set of data comprising a same logic value to represent the failure of the syndrome check operation; and transmit the second set of data based at least in part on generating the second set of data. However, Meaney in an analogous art teaches generating a set of data comprising a same logic value to represent an uncorrectable error condition (end of paragraph 42).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to generate a set of data comprising a same logic value to represent the failure of the syndrome check operation of Sharma. This modification would have been obvious for one of ordinary skill in the art at the time of filing because it was an alternative way to represent syndrome failure, as shown by Meaney.
Claim(s) 9 are rejected under 35 U.S.C. 103 as being unpatentable over Sharma in view of Drake
As per claim 9: Sharma teaches the memory device of claim 2. Not explicitly disclosed is wherein the processing circuitry is further configured to cause the memory device to: disable a mode associated with performing the syndrome check operation based at least in part on a received request after transmitting the first set of error control bits, wherein performing the syndrome check operation is based at least in part on the mode being enabled. However, Drake in an analogous art teaches disabling a syndrome check operation upon detecting an uncorrectable error (Fig. 2, 82), and performing ECC syndrome computation when ECC is not disabled (Fig. 2, 88-86).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to disable the ECC syndrome circuitry of Sharma when an uncorrectable error is detected. This modification would have been obvious for one of ordinary skill in the art at the time of filing because ECC and syndrome computations would have been unnecessary for uncorrectable data.
Claim(s) 11 are rejected under 35 U.S.C. 103 as being unpatentable over Sharma in view of Ranganathan et al (US Pat. Pub. 2021/0149763; hereinafter referred to as Ranganathan).
As per claim 11:
Sharma teaches the memory device of claim 2. Not explicitly disclosed is wherein the first set of error control bits indicates an uncorrectable error in the set of data. However, Ranganathan in an analogous art teaches a single error detecting code (paragraph 370).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to use the error detecting code of Ranganathan in the system of Sharma. This modification would have been obvious for one of ordinary skill in the art at the time of filing because any known error code such as that of Ranganathan could have been used in Sharma without changing the principle of operation.
Claim(s) 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Sharma in view of Hauck.
As per claim 12: Sharma teaches the memory device of claim 2. Not explicitly disclosed is wherein the first set of error control bits is associated with a non-aliasing error. However, Hauck in an analogous art teaches a non-aliasing single bit error code (col. 4, lines 50-60).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to use the error code of Hauck in the system of Sharma. This modification would have been obvious for one of ordinary skill in the art at the time of filing because any known error code such as that of Hauck could have been used in Sharma without changing the principle of operation.
As per claim 13:
Sharma teaches the memory device of claim 2. Not explicitly disclosed is wherein the first set of error control bits further comprise additional information for detecting an occurrence of a failure of the syndrome check operation. However, Hauck in an analogous art teaches an error code utilizing a parity to indicate whether a double bit error occurred (col. 5, lines 4-5).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to utilize the parity of Hauck in the system of Sharma. This modification would have been obvious for one of ordinary skill in the art at the time of filing because it would have been useful in indicating that a double bit error occurred.
Allowable Subject Matter
Claim 10 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: None of the prior art of record teach or fairly suggest wherein the processing circuitry is further configured to cause the memory device to: receive, based at least in part on disabling the mode associated with performing the syndrome check operation, a second read command associated with the set of data; generate, as part of a second error control operation, the second set of error control bits; and transmit the set of data and the second set of error control bits based at least in part on generating the second set of error control bits; particularly in combination with each and every limitation of intervening claim 9 and parent claim 1.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure and directed to ECC syndrome checking in memory.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVE N NGUYEN whose telephone number is (571)272-7214. The examiner can normally be reached M-F 9-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mark Featherstone can be reached at 571-270-3750. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/STEVE N NGUYEN/Primary Examiner, Art Unit 2111