Prosecution Insights
Last updated: August 17, 2026
Application No. 18/795,998

ARCHITECTURE OF THREE-DIMENSIONAL MEMORY DEVICE AND METHODS REGARDING THE SAME

Non-Final OA §103
Filed
Aug 06, 2024
Priority
May 03, 2019 — divisional of 11/244,855 +1 more
Examiner
VO, TUYEN KIM
Art Unit
Tech Center
Assignee
Micron Technology Inc.
OA Round
1 (Non-Final)
78%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
96%
With Interview

Examiner Intelligence

Grants 78% — above average
78%
Career Allowance Rate
941 granted / 1201 resolved
+18.4% vs TC avg
Strong +18% interview lift
Without
With
+17.8%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 11m
Avg Prosecution
26 currently pending
Career history
1215
Total Applications
across all art units

Statute-Specific Performance

§101
1.6%
-38.4% vs TC avg
§103
51.2%
+11.2% vs TC avg
§102
23.8%
-16.2% vs TC avg
§112
13.0%
-27.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1201 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claims 2 and 21 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 10 of U.S. Patent No. 12,068,192. Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1 and 10 of U.S. Patent No. 12,068,192 cover and encompass the limitations of the respective claims 2 and 21 of the instant application. Moreover, because omission element(s) in the claims would make the claims in the instant application broader, it would have been obvious to one of ordinary skill in the art at the time of the invention to modify the claim(s) in the U.S. Patent No. 12,068,192 to as now recited in the instant application since it is just merely an obvious variation of the claims. Furthermore, it is well settled that omission of an element and it function is an obvious expedient if the remaining elements perform the same function as before. In re Karlson, 163 USPQ 184 (CCPA 1963). In light of the foregoing discussion, the claims 2 and 21 of the instant application are rejected as obvious double patenting over the claims 1 and 10, respectively, of U.S. Patent No. 12,068,192. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim(s) 2-11 and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nardi et al. (US 2019/0115391, cited by applicant) in view of Jeong et al. (US 2017/0244031). Regarding claim 2, Nardi teaches an apparatus (figs. 7A-7D), comprising: a plurality of contacts (VTFT 731) associated with a plurality of digit lines (GBL 733) extending through a substrate (D714) and arranged in a geometric pattern ([0076]); a dielectric material (white space between the WL, figs. 11K and 11L) separating a first set of a plurality of word line plates (WL 1 and WL 3) from a second set of the plurality of word line plates (WL 2 and WL 4); a plurality of pillars (VBL 721) formed over the plurality of contacts and arranged in a geometric pattern, each pillar of the plurality of pillars coupled with a contact of the plurality of contacts (VBL 721 surrounded by an OTS 723 and C 725); and a plurality of storage elements (PCM 701), each comprising a chalcogenide material (Ge2Sb2Te5, GST, [0050] and [0058]) positioned between at least one of the plurality of word line plates, at least one pillar, and at least one dielectric layer ([0070]-[0079] and [0104]-[0119]). Nardi fails to teach the plurality of pillars (VBL 721, [0071] and [0072]) comprises circular pillars. However, Jeong teaches memory cells have various pillar shapes, i.e. circular pillars, elliptical pillar, etc. ([0047] and [0136]). In view of Jeong’s teaching, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Nardi by incorporating the teaching as taught by Jeong since it is just a matter of design option for selecting various shape for the pillars (see Jeong: [0047]). Regarding claim 3, Nardi as modified by Jeong teaches all subject matter claimed as applied above. Nardi further teaches wherein the plurality of circular pillars (VBL 721) is coupled with a plurality of selectors (VTFT 731) positioned below the substrate or above the plurality of word line plates (figs. 7B-7D and [0072]). Regarding claim 4, Nardi as modified by Jeong teaches all subject matter claimed as applied above. Nardi further teaches a conformal material extending between a first chalcogenide material and a second chalcogenide material in recesses between word line plates of the first set and contacting the dielectric material ([0108]). Regarding claim 5, Nardi as modified by Jeong teaches all subject matter claimed as applied above. Both Nardi and Jeong further teach wherein a circular pillar of the plurality of circular pillars further comprises a barrier layer contacting at least portions of the chalcogenide material and a conductive material contacting the barrier layer and configured as a digit line (Nardi: [0073] and [0108]. Jeong: [0040] and [0069]). Regarding claim 6, Nardi as modified by Jeong teaches all subject matter claimed as applied above. Nardi further teaches wherein at least one word line plate of the plurality of word line plates comprises a conductive material (figs. 7A, 7B and [0075]). Regarding claim 7, Nardi as modified by Jeong teaches all subject matter claimed as applied above. Both Nardi and Jeong further teach wherein the plurality of contacts is arranged in a staggered pattern or a grid pattern (Nardi: fig. 7A. Jeong: figs. 18-19). Regarding claim 8, Nardi as modified by Jeong teaches all subject matter claimed as applied above. Both Nardi and Jeong further wherein the plurality of contacts is arranged such that a respective contact of the plurality of contacts is surrounded by six contacts of the plurality of contacts in a staggered pattern (Nardi: figs. 7A-7D and 11I-11L. Jeong: figs. 18-19). Regarding claims 9 and 10, Nardi as modified by Jeong teaches all subject matter claimed as applied above. Both Nardi and Jeong further wherein the plurality of contacts are arranged in a staggered pattern such that the plurality of contacts are adjacent to one another in a first direction and are not adjacent to one another in a second direction and further limitations as claimed (Nardi: figs. 7A-7D and 11I-11L. Jeong: figs. 18-19). Regarding claim 11, Nardi as modified by Jeong teaches all subject matter claimed as applied above. Both Nardi and Jeong further wherein a first spacing between a first pair of contacts of the plurality of contacts in a first direction is different than a spacing between a second pair of contacts of the plurality of contacts in the first direction (figs. 7A-7D and 11I-11L. Jeong: figs. 18-19). Regarding claim 21, Nardi teaches an apparatus (figs. 7A-7D), comprising: a plurality of contacts (VTFT 731) associated with a plurality of digit lines (GBL 733) extending through a substrate (D714) and arranged in a geometric pattern ([0076]); a plurality of first word lines (WL 1 and WL 3) stacked in a first direction above the substrate; a plurality of second word lines (WL 2 and WL 4) stacked in the first direction above the substrate; a dielectric material (white space between the WL, figs. 11K and 11L) separating the plurality of first word lines from the plurality of second word lines; a plurality of pillars (VBL 721) formed over the plurality of contacts and arranged in a geometric pattern, each pillar of the plurality of pillars coupled with a contact of the plurality of contacts (VBL 721 surrounded by an OTS 723 and C 725); and a plurality of first storage elements (PCM 701) each comprising a chalcogenide material (Ge2Sb2Te5, GST, [0050] and [0058]) positioned between at least one first word line of the plurality of first word lines, at least one pillar, and at least a portion of the dielectric material; and a plurality of second storage elements (another PCM 701) each comprising a chalcogenide material (Ge2Sb2Te5, GST, [0050] and [0058]) positioned between at least one second word line of the plurality of second word lines, at least one pillar, and at least a portion of the dielectric material ([0070]-[0079] and [0104]-[0119]). Nardi fails to teach the plurality of pillars (VBL 721, [0071] and [0072]) comprises circular pillars. However, Jeong teaches memory cells have various pillar shapes, i.e. circular pillars, elliptical pillar, etc. ([0047] and [0136]). In view of Jeong’s teaching, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Nardi by incorporating the teaching as taught by Jeong since it is just a matter of design option for selecting various shape for the pillars (see Jeong: [0047]). Claim(s) 12-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nardi in view of Jeong and Rupp (US 6,091,094). Regarding claim 12, Nardi teaches an apparatus (figs. 7A-7D), comprising: a plurality of contacts (VTFT 731) associated with a plurality of digit lines (GBL 733) extending through a substrate (D714) and arranged in a geometric pattern ([0076]); a dielectric material (white space between the WL, figs. 11K and 11L) separating a first set of planes (WL 1 and WL 3) of a conductive material from a second set of planes (WL 2 and WL 4) of the conductive material; a plurality of pillars (VBL 721) formed over the plurality of contacts and arranged in a geometric pattern, each pillar of the plurality of pillars coupled with a contact of the plurality of contacts (VBL 721 surrounded by an OTS 723 and C 725); and a plurality of storage elements (PCM 701) each comprising a chalcogenide material (Ge2Sb2Te5, GST, [0050] and [0058]) positioned between at least one plane of the first set of planes or the second set of planes of the conductive material, at least one pillar, and at least one dielectric layer ([0070]-[0079] and [0104]-[0119]). Nardi fails to teach hexagonal pattern and the plurality of pillars comprises circular pillars. However, Rupp further teaches memory device comprises a plurality of contacts associated with plurality of digit lines extending through a substrate and arranged in a hexagonal pattern (col. 5, lines 48-60, col. 7, lines 38-50 and col. 10, lines 33-48). Moreover, Jeong teaches memory cells have various pillar shapes, i.e. circular pillars, elliptical pillar, etc. ([0047] and [0136]). In view of Rupp’s and Jeong’s teachings, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Nardi by incorporating the teachings as taught by Rupp and Jeong since it is just a matter of design option for selecting various shape for memory device. Regarding claim 13, Nardi as modified by Rupp and Jeong teaches all subject matter claimed as applied above. Nardi further teaches wherein the plurality of circular pillars (VBL 721) is coupled with a plurality of selectors (VTFT 731) positioned below the substrate or above the first set of planes and the second set of planes of the conductive material (figs. 7B-7D and [0072]). Regarding claim 14, Nardi as modified by Rupp and Jeong teaches all subject matter claimed as applied above. Nardi further teaches a conformal material extending between a first chalcogenide material and a second chalcogenide material in recesses between one or more planes of the first set of planes of the conductive material and contacting the dielectric material ([0108]). Regarding claim 15, Nardi as modified by Rupp and Jeong teaches all subject matter claimed as applied above. Both Nardi and Jeong further teach wherein a circular pillar of the plurality of circular pillars further comprises a barrier layer contacting at least portions of the chalcogenide material and a conductive material contacting the barrier layer and configured as a digit line (Nardi: [0073] and [0108]. Jeong: [0040] and [0069]). Regarding claim 16, Nardi as modified by Rupp and Jeong teaches all subject matter claimed as applied above. Nardi further teaches wherein the first set of planes and the second set of planes of the conductive material comprise a plurality of word line plates (figs. 7A, 7B and [0075]). Regarding claim 17, Nardi as modified by Rupp and Jeong teaches all subject matter claimed as applied above. Both Nardi and Jeong further wherein the plurality of contacts is arranged such that a respective contact of the plurality of contacts is at least partially surrounded by six contacts of the plurality of contacts in the hexagonal pattern (Nardi: figs. 7A-7D and 11I-11L. Jeong: figs. 18-19). Regarding claims 18 and 19, Nardi as modified by Rupp and Jeong teaches all subject matter claimed as applied above. Both Nardi and Jeong further wherein the plurality of contacts are adjacent to one another in a first direction and are not adjacent to one another in a second direction and further limitations as claimed (Nardi: figs. 7A-7D and 11I-11L. Jeong: figs. 18-19). Regarding claim 20, Nardi as modified by Rupp and Jeong teaches all subject matter claimed as applied above. Both Nardi and Jeong further wherein a first spacing between a first pair of contacts of the plurality of contacts in a first direction is different than a spacing between a second pair of contacts of the plurality of contacts in the first direction (figs. 7A-7D and 11I-11L. Jeong: figs. 18-19). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. References: Fantini et al. (US 2020/0203429); Jeong et al. (US 2019/0172502); Ko (US 2019/0131348); Lee et al. (US 10,008,539); Nowak et al. (US 2015/0115345) Katine et al. (US 9,941,331) and Doda et al. (US 2016/0276360) are cited because they are related to memory apparatus. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Tuyen Kim Vo whose telephone number is (571)270-1657. The examiner can normally be reached Mon-Thurs: 8AM-6:30PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Paik can be reached at 571-272-2404. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TUYEN K VO/Primary Examiner, Art Unit 2876
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Prosecution Timeline

Aug 06, 2024
Application Filed
Aug 05, 2026
Non-Final Rejection mailed — §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
78%
Grant Probability
96%
With Interview (+17.8%)
1y 11m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1201 resolved cases by this examiner. Grant probability derived from career allowance rate.

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