DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This office action is in response to the amendment filed on 03/25/2026. Claims 1-20 are pending. Claims 1-6, 8-15, and 19 are amended. Examiner notes that claim 14 line 10 appears to have replaced the word “a” with --the-- and the last line replaced “types” with “type” without using the appropriate strikethrough and underline markings, which are non-compliant amendments. Applicant is requested to ensure there are no other non-compliant amendments.
Response to Arguments
Applicant’s arguments, see Remarks pages 9-10, filed 03/25/2026, with respect to the rejection of claim 1 have been fully considered and are persuasive. Specifically, the argument that Tran and Wu do not teach claim 1 as amended is persuasive. The 103 rejection of claim 1 has been withdrawn. However, the amendments to claim 1 raise written description issues and a 112(a) rejection is given below.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-12 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 recites “a branch target buffer (BTB) that stores, for a loop, a loop type and a loop count, the BTB including a plurality of BTB entries… each of the BTB entries including branch information comprising the loop type and the loop count”. This limitation describes a BTB storing the same loop type and loop count in each of its entries, however, the specification does not describe a BTB that stores the same loop type and loop count in each entry. Fig. 7 of the drawings show the BTB storing different loop types and loop count in each entry.
Claims dependent on claim 1 are rejected based on their dependence.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 7 and 10-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 7 recites “the first instruction queue” in line 1. There is insufficient antecedent basis for this limitation as the claim does not introduce a first instruction queue. For purposes of examination this will be interpreted as referring to the instruction queue introduced in claim 1.
Claim 10 recites “the loop instruction” in line 3. There is insufficient antecedent basis for this limitation as the claim does not introduce a loop instruction. For purposes of examination this will be interpreted as any loop instruction.
Claim 11 recites “the dual basic-block loop is written into the branch target buffer” in lines 3-4. However, [0023] of the specification discloses that “The BTB 26 is a cache array which comprises of a tag array and data array. The tag array comprises of plurality of entries of start addresses and the data array comprises of target address, ending address, branch type which includes loop prediction, and predicted loop count.” It is thus unclear whether the BTB stores the dual basic-block loop itself or if it stores information about the dual basic-block loop as described in [0023]. For purposes of examination this will be interpreted as the BTB storing information about the dual basic-block loop.
Claim 12 recites “the dual basic-block loop is written into the branch target buffer” in lines 4-5. However, [0023] of the specification discloses that “The BTB 26 is a cache array which comprises of a tag array and data array. The tag array comprises of plurality of entries of start addresses and the data array comprises of target address, ending address, branch type which includes loop prediction, and predicted loop count.” It is thus unclear whether the BTB stores the dual basic-block loop itself or if it stores information about the dual basic-block loop as described in [0023]. For purposes of examination this will be interpreted as the BTB storing information about the dual basic-block loop.
Claim 13 recites “the instruction issue unit” in line 9. There is insufficient antecedent basis for this limitation as the claim does not introduce an instruction issue unit.
Claim 13 recites “the loop instructions” in line 11. There is insufficient antecedent basis for this limitation as the claim does not introduce loop instructions.
Claim 13 recites “the corresponding plurality of iterations” in lines 13-14. There is insufficient antecedent basis for this limitation as the claim does not introduce a corresponding plurality of iterations.
Claim 14 recites “the dual basic-block loop” in line 7. There is insufficient antecedent basis for this limitation as the claim does not introduce a dual basic-block loop.
Claim 14 recites “a basic block of instructions” in line 8. It is unclear if this is the same as the basic block of instructions introduced in line 6 or if they are different.
Claim 14 recites “the dual basic-block loop” in line 9. There is insufficient antecedent basis for this limitation as the claim does not introduce a dual basic-block loop.
Claim 14 recites “the loop” in line 10. There is insufficient antecedent basis for this limitation as the claim does not introduce a loop.
Claim 14 recites “the dual basic-block loop” in line 11. There is insufficient antecedent basis for this limitation as the claim does not introduce a dual basic-block loop.
Claim 14 recites “the dual basic-block loop” in line 13. There is insufficient antecedent basis for this limitation as the claim does not introduce a dual basic-block loop.
Claim 14 recites “the loop type of the dual-basic block loop” in line 13. There is insufficient antecedent basis for this limitation as the claim does not introduce a dual-basic block loop having loop types.
Claim 15 recites “the loop” in line 3. There is insufficient antecedent basis for this limitation in the claim.
Claim 16 recites “the loop” in line 2 and line 4. There is insufficient antecedent basis for this limitation in the claim.
Claim 16 recites “the loop instructions” in line 2. There is insufficient antecedent basis for this limitation as the claim does not introduce loop instructions.
Claim 17 recites “the loop” in line 2. There is insufficient antecedent basis for this limitation in the claim.
Claim 18 recites “the first basic block loop” in line 2 and line 4. There is insufficient antecedent basis for this limitation as the claim does not introduce a first basic block loop.
Claim 18 recites “the second basic block in the BTB” in line 4-5. There is insufficient antecedent basis for this limitation as the claim does not introduce a second basic block in the BTB.
Claim 19 recites “the second basic block loop” in line 3. There is insufficient antecedent basis for this limitation as the claim does not introduce a second basic block loop.
Claim 19 recite “an entry of a branch target buffer” in lines 2-3. It is unclear whether this refers to the same entry and branch target buffer introduced in claim 18 lines 2-3 or if they are different.
Claim 19 recites “the BTB” in lines 4-5. It is unclear whether this refers to the BTB introduced in lines 3-4 or the BTB introduced in claim 18.
Claim 19 recites “the loop” in line 4. There is insufficient antecedent basis for this limitation as the claim does not introduce a loop prediction.
Claim 20 recites “the branch misprediction” in line 2. There is insufficient antecedent basis for this limitation as the claim does not introduce a branch misprediction.
Claim 20 recites “the dual basic-block loop” in line 3. There is insufficient antecedent basis for this limitation in the claim.
Claim 20 recites “the branch target buffer” in line 3-4. There is insufficient antecedent basis for this limitation as the claim does not introduce a branch target buffer.
Claims dependent on rejected base claims are further rejected based on their dependence.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 14-16 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Tran US 2007/0113059 in view of Wu “Instruction Fetch Power Reduction Using Forward-Branch and Subroutine Bufferable Innermost Loop Buffer”.
Regarding claim 14, Tran teaches:
14. A computer program product stored on a non-transitory computer readable storage medium and including computer system instructions for causing a computer system to execute a method that is executable by a processor, the method generating a loop count ([0033] describes incrementing a counter when the stored PC and target address matches the pc and target address for a backwards taken conditional branch, which generates a predicted loop count), the method comprising:
sending basic blocks of instructions to an instruction queue based on detecting the loop (Tran [0036-[0037]: based on detecting the loop at step 312, instructions are fetched, transferred into, and executed directly from the instruction queue)
Tran does not teach:
the method detecting a dual basic-block loop type in a series of instructions; the method comprising:
identifying in the series of instructions, a basic block of instructions and classifying the basic block of instructions as a first basic block of the dual basic-block loop;
identifying in the series of instructions, a basic block of instructions and classifying the basic block of instructions as a second basic block of the dual basic-block loop
classifying the loop into one of a plurality of loop types based on a first or second basic block of the dual basic-block loop; and
sending the first and second basic blocks of instructions to an instruction queue based on the loop types of the dual basic-block loop;
However, Wu teaches:
identifying in the series of instructions, a basic block of instructions and classifying the basic block of instructions as a first basic block of the dual basic-block loop (Wu sec. 3.1.2.: by recording the FD bit of a first forward branch in a loop, a basic block is classified as a first basic block of a dual basic block loop);
identifying in the series of instructions, a basic block of instructions and classifying the basic block of instructions as a second basic block of the dual basic-block loop (Wu sec. 3.1.2.: by recording the FD bit of a second forward branch in the loop, a basic block is classified as a second basic block of a dual basic block loop);
classifying the loop into one of a plurality of loop types based on a first or second basic block of the dual basic-block loop (the FD-bits of the forward branches of basic blocks of the loop classify the loop into a loop type corresponding to the directions of the forward branches of the basic blocks of the loop).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the processor of Tran to identify and classify basic blocks of the loop by predicting forward branches in the loop and recording the prediction result into FD-bits of the BTB as taught by Wu such that the FD-bits of the combination would classify the loop into one of a plurality of loop types and the combination would send the loop instructions/basic blocks of the loop to the instruction queue based on the FD-bits/loop type. One of ordinary skill in the art would have been motivated to make this modification to increase utilization of the instruction queue/loop buffer, see Wu sec. 1 par. 3.
Regarding claim 15, Tran in view of Wu teaches:
15. The computer program product of claim 14 wherein the method further comprises:
generating the loop count for the loop [0033] describes incrementing a counter when the stored PC and target address matches the pc and target address for a backwards taken conditional branch, which generates a predicted loop count); and
generating a program counter calculation as a function of the loop count ([0027] describes using an offset to set up a start pointer for the instruction queue and [0029] describes fetching instructions into the instruction queue with the start pointer, this indicates that the program counter for instructions of the loop is calculated/generated based on the offset, which is based on the predicted loop count being equal to a threshold, see [0036]).
Regarding claim 16, Tran in view of Wu teaches:
16. The computer program product of claim 14 wherein the method further comprises:
if the loop comprises the dual basic-block loop type, virtually unrolling the loop instructions in the instruction queue (Tran [0029] describes that executing instructions from the instruction queue until the loop is complete, thus by providing instructions of the loop iterations until the loop is complete, the instruction queue virtually unrolls instructions in the loop iterations to the next stage); and
sending instructions from a plurality of iterations of the loop to a next pipeline stage (Tran [0020] describes sending instructions from the instruction queue to the decode unit, which is a next pipeline stage).
Regarding claim 20, Tran in view of Wu teaches:
20. The computer program product of claim 14
Tran in view of Wu, as currently mapped, does not teach:
ignoring the branch misprediction related to any branch within the first or second basic block of the dual basic-block loop once the dual basic-block loop is written into the branch target buffer.
However, Wu sec 3.1.4 teaches fetching instructions from the cache without flushing instructions in the loop buffer when there is a misprediction.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the instruction queue of Tran to ignore mispredictions due to branches in basic blocks of the loop by not flushing as taught by Wu once the loop is detected/written to the BTB. One of ordinary skill in the art would have been motivated to make this modification to avoid flushing instructions in the instruction queue that may be useful in the future (i.e., if the execution path returns to the loop).
Claims 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Tran US 2007/0113059 in view of Wu “Instruction Fetch Power Reduction Using Forward-Branch and Subroutine Bufferable Innermost Loop Buffer” and Wiencke US 2015/0212820.
Regarding claim 17, Tran in view of Wu teaches:
17. The computer program product of claim 16
Tran in view of Wu does not teach:
writing sequential instructions after the loop into the instruction queue.
However, Wiencke [0034] teaches loading post-loop instructions from memory into an instruction storage of a fetch buffer (analogous to the instruction queue of Tran) when the loop is complete.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the instruction queue of Tran to store sequential instructions after the loop when the loop is complete as taught by Wiencke. One of ordinary skill in the art would have been motivated to make this modification to improve utilization of the instruction queue and to relax timing constraints between the cache module and the decode unit for sequential instructions after the loop.
Regarding claim 18, Tran in view of Wu and Wiencke teaches:
18. The computer program product of claim 17 wherein the method further comprises:
writing prediction bits associated with the first basic block loop to an entry of a branch target buffer (BTB) to cause the BTB to use a target address field of the BTB to access a basic block in the BTB that comprises the first basic block loop to access the second basic block in the BTB (Tran [0030]: the BTB stores the offset/entry to the loop, which are prediction bits associated with the first basic block that causes the BTB to use a target address field (the field that stores the offset) to access the first basic block, which may then execute to a forward branch that accesses the second basic block in the combination).
Prior Art Considerations
While no prior art rejection is currently given for claims 1-13 and 19, these claims are currently rejected under 112(a)/(b) and are thus not allowable at the current point. The prior art considerations for claims 13 and 19 are the same as the prior art considerations given in the Non-Final Rejection dated 09/25/2025. The following prior art considerations are given for claims 1-12.
The known prior art of record, taken alone or in combination, was not found to teach, in combination with other limitations in the claim, a BTB including a plurality of entries that stores the same loop type and loop count in each entry, as described in claim 1.
The closest prior art of record was found to be Tran US 2007/0113059 and Wu “Instruction Fetch Power Reduction Using Forward-Branch and Subroutine Bufferable Innermost Loop Buffer”. While Tran teaches a BTB storing a loop count in each entry, see [0026] and [0030], and Wu teaches a BTB storing a forward direction bit in each entry, see sec. 3.1, these references taken alone or in combination do not teach a BTB having a plurality of entries that store the same loop type and loop count as required by claim 1.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
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/KASIM ALLI/Examiner, Art Unit 2182
/JYOTI MEHTA/ Supervisory Patent Examiner, Art Unit 2183
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