Prosecution Insights
Last updated: October 04, 2026
Application No. 18/796,200

SEMICONDUCTOR DEVICE

Non-Final OA §112
Filed
Aug 06, 2024
Priority
Oct 28, 2021 — TW 110140156 +1 more
Examiner
RAHMAN, KHATIB A
Art Unit
Tech Center
Assignee
Powerchip Semiconductor Manufacturing Corporation
OA Round
1 (Non-Final)
91%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
96%
With Interview

Examiner Intelligence

Grants 91% — above average
91%
Career Allowance Rate
432 granted / 474 resolved
+31.1% vs TC avg
Minimal +5% lift
Without
With
+5.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
23 currently pending
Career history
491
Total Applications
across all art units

Statute-Specific Performance

§103
49.4%
+9.4% vs TC avg
§102
27.2%
-12.8% vs TC avg
§112
18.5%
-21.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 474 resolved cases

Office Action

§112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 1-8 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 1 (in lines 7-10) recites “and a width of one of the electrodes is smaller as the one of the electrodes is farther away from the top gate, wherein a width of the top gate is smaller than a width of an electrode of the electrodes that is closest to the top gate”. The limitations “one of the electrodes” and “an electrode of the electrodes” are not clearly understood. It was unclear if each was referring to an electrode of “a plurality of electrode” as recited in claim 1 (in lines 6-7) or different electrode. For examination purpose, examiner is interpreting it as “and a width of one of the electrodes of the plurality of electrodes is smaller as the one of the electrodes of the plurality of electrodes is farther away from the top gate, wherein a width of the top gate is smaller than a width of an electrode of the plurality of electrodes that is closest to the top gate”. Claim 1 further teaches “a substrate, having a trench” in line 2. The limitation “a trench” is not clearly understood while correlating it with the limitation “adjacent trenches” in claim 5 in line 2 (which requires plurality of trenches). Fig. 10 shows substrate 100 having plurality of trenches and substrate region 200 disposes in the substrate 100 and between adjacent trenches of the plurality of trenches. Accordingly, for examination purpose, examiner is interpreting the associated limitations in claim 1 in line 2 as “a substrate, having a plurality of trenches” To be consistent with claim 1 in line 2 interpretation as stated above, examiner is interpreting claim 5 line 2 as “a substrate region, disposed in the substrate and between adjacent trenches of the plurality of trenches” and interpreting claim 8 as “wherein a distance between the first electrode and a sidewall of [[the]] a trench of the plurality of trenches is 4000 Å to 4500 Å, a distance between the second electrode and the sidewall of the trench of the plurality of trenches is 3000Å to 3500Å, and a distance between the third electrode and the sidewall of the trench of the plurality of trenches is 2000 Å to 2500 Å”. Claims 2-8 are rejected being dependent on claim 1. Claim 2 further recites “….wherein the second conductive layer is disposed on the first conductive layer……” . It is unclear what spatial relationship is intended by “disposed on” and how this limitation is to be interpreted consistently with claim 1. In particular, interpreting from Fig. 10, “wherein the bottom gate comprises a first conductive layer (140) and a second conductive layer (130), wherein the second conductive layer (130) is disposed on the first conductive layer (140), and the second conductive layer (130) comprises the electrodes (132, 134 & 136)”, it appears to require element 130 to be disposed on element 140 in an orientation/direction opposite to that required by claim 1 (e.g. a top gate (140) disposed on the bottom gate (130)). Accordingly, the scope of the claim cannot be reasonable ascertained. Claim 2 further recites “….and the second conductive layer comprises the electrodes”. The limitation “the electrodes” is not clearly understood. It is unclear if it was referring to “a plurality of electrodes” as recited in claim 1 (in lines 6-7) or different electrodes. According to above, for examination purpose, examiner is interpreting the entire claim 2 limitation as “wherein the bottom gate comprises a first conductive layer and a second conductive layer, wherein the [[second]] first conductive layer is disposed on the [[first]] second conductive layer, and the second conductive layer comprises the plurality of electrodes”. Allowable Subject Matter Claims 1-8 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action. With respect to claim 1, the prior art of record does not appear to teach, suggest, or provide motivation for combination to following limitation: “wherein a width of the top gate is smaller than a width of an electrode of the plurality of electrodes that is closest to the top gate” Regarding claim 1, SHIBIB et al. (US 2020/0243656 A1) teaches, PNG media_image1.png 637 491 media_image1.png Greyscale A semiconductor device (200, Fig. 2, para [0047]), comprising: a substrate (including 140 & 120 , para [0037]), having a trench (230, para [0048]); and a gate structure, disposed in the trench, comprising: a shielded gate (SHILED 201 which is analogous to shield gate 101 in Fig. 1, para [0039]), comprising a bottom gate (including A, B & C as marked above) and a top gate (including D as marked above) disposed on the bottom gate, wherein the bottom gate comprises a step structure (step structure formed by A, B & C as seen) consisting of a plurality of electrodes (A, B & C), and a width of one of the electrodes is smaller as the one of the electrodes is farther away from the top gate (as seen width of A,B, C is smaller farther away from D), a control gate (111, para [0039]), disposed on the shielded gate; a first ……layer (layer of trench oxide 225 between 201 and 120 as marked), disposed between the shielded gate and the substrate; a second …… layer (layer of trench oxide 225 between 111 and 201 as marked) , disposed on the shielded gate to separate the shielded gate from the control gate; and a third …… layer(layer trench 225 between 111 and 120 as marked), disposed between the control gate and the substrate. But SHIBIB fails to teach or suggest, trench oxide 225 is an insulating layer wherein a width of the top gate is smaller than a width of an electrode of the electrodes that is closest to the top gate . But SHIBIB additionally teaches, shield insulating material 103, 104 & 105 are disposed between shielded gate 101 and substrate 120 , between shielded gate 101 and control gate 111 and between control gate 111 and substrate 120 respectively (Fig. 1). It would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to modify SHIBIB such that trench oxide 225 are made of insulating material, according to teaching of SHIBIB above, in order to insulate the shield electrode 201 from substrate, to provide an inter-electrode insulating material to separate the shield electrode from control electrode, and to form a gate insulating material for the control electrode 111, as taught by SHIBIB (para [0040], Fig. 1). However, SHIBIB still fails to teach, wherein a width of the top gate is smaller than a width of an electrode of the electrodes that is closest to the top gate The other cited arts, either alone or in combination, fails to cure deficiencies of SHIBIB. Claims 2-8 would be allowable being dependent on claim 1. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHATIB A RAHMAN whose telephone number is (571)270-0494. The examiner can normally be reached on MON-FRI 8:00 am- 5:00 pm (Arizona). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor Steven Loke, can be reached on (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /K.A.R/Examiner, Art Unit 2818 /STEVEN H LOKE/ Supervisory Patent Examiner, Art Unit 2818
Read full office action

Prosecution Timeline

Aug 06, 2024
Application Filed
Sep 01, 2026
Non-Final Rejection mailed — §112 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
91%
Grant Probability
96%
With Interview (+5.0%)
2y 2m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 474 resolved cases by this examiner. Grant probability derived from career allowance rate.

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