Prosecution Insights
Last updated: April 19, 2026
Application No. 18/796,328

LINK STATE CONTROL METHOD AND DATA STORAGE SYSTEM

Non-Final OA §102§103
Filed
Aug 07, 2024
Examiner
BIRKHIMER, CHRISTOPHER D
Art Unit
2138
Tech Center
2100 — Computer Architecture & Software
Assignee
Acer Incorporated
OA Round
3 (Non-Final)
75%
Grant Probability
Favorable
3-4
OA Rounds
2y 11m
To Grant
82%
With Interview

Examiner Intelligence

Grants 75% — above average
75%
Career Allow Rate
370 granted / 496 resolved
+19.6% vs TC avg
Moderate +8% lift
Without
With
+7.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 11m
Avg Prosecution
30 currently pending
Career history
526
Total Applications
across all art units

Statute-Specific Performance

§101
2.8%
-37.2% vs TC avg
§103
43.1%
+3.1% vs TC avg
§102
21.6%
-18.4% vs TC avg
§112
27.2%
-12.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 496 resolved cases

Office Action

§102 §103
DETAILED ACTION The current Office Action is in response to the papers submitted 01/12/2026. Claims 1 - 10 are pending. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1 – 2, 5 – 7, and 10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lenovo (NVMe SSD transmission mode dynamically changes with AMD new PSPP (PCIE Speed Power Policy) design) referred to as Lenovo in view of Choi (Pub. No.: US 2023/0359399) referred to as Choi. Regarding claim 1, Lenovo teaches a link state control method for a for a host system [Page 2, Applicable Systems; The systems are the hosts] connected to a to a memory device [Page 2, System Is Configured With; The memory is NVMe SSD in the host], the link state control method [Page 1, Symptom; The PCIe is a connection to a memory and the AC mode is a dynamic method of adjusting the connection to the memory based on load] comprising: establishing a connection [Page 1; Symptom; The PCIe Generation is a connection between the memory and the host system] between the host system [Page 2, Applicable Systems] and the memory device [Page 2, System Is Configured With]; setting a link state adopted by the connection [Page 1; Symptom; The PCIe Generation is a connection between the memory and the host system] to one of a plurality of candidate link states [Page 1, Symptom; Gen1 – Gen3 are link states based on speed the SSD connection is set to], wherein setting the link state adopted by the connection to the one or the candidate link states [Page 1, Symptom; Gen1 – Gen3 are link states based on speed the SSD connection is set to]comprises: switching the link state adopted by the connection from one of Gen 1 to Gen 5 of high-speed peripheral component interconnect express standard to another one of the Gen 1 to the Gen 5 of the high-speed peripheral component interconnect express standard [Page 1, Symptom; The connection state switches between Gen 1, Gen 2, and Gen 3 dynamically based on the load on the SSD. The connection state is related to a speed of the connection]. However, Lenovo may not specifically disclose the limitation(s) of detecting a temperature of the memory device through the connection and setting a link state according to the temperature. Choi discloses detecting a temperature of the memory device [100, Fig 1; 10, Figs 5, 8, and 10] through the connection [Figs 8 and 10; S1130, Fig 11; Paragraphs 0012, 0018, 0137, 0164 – 0191; The host detects the temperature through the AFC Frame sent through the connection between the host and the memory device] and setting a link state according to the temperature [Paragraphs 0137 and 0170; The speed is a link state between the host and the memory device and the host changes the speed based on a temperature reading. The ability to change it shows the link state is set to one of a plurality of possible states]. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Choi in Lenovo, because it allows temperature to be a deciding factor of when to change the link state to prevent damage due to overheating. Regarding claim 2, Choi teaches the step of setting the link state adopted by the connection to one of the plurality of candidate link states according to the temperature [Paragraph 0137; The speed is a link state between the host and the memory device and is changed based on a temperature reading. The ability to change it shows the link state is set to one of a plurality of possible states] comprises: determining whether the temperature falls within a target temperature range among a plurality of candidate temperature ranges [S910 and S930, Fig 9; Paragraph 0137; The temperature exceeding a threshold shows the system determines if the temperature falls within at least two candidate temperature ranges]; and in response to the temperature falling within the target temperature range, setting the link state adopted by the connection to a target link state corresponding to the target temperature range among the plurality of candidate link states [Paragraph 0137; When the temperature reaches falls within in certain range the speed is adjusted accordingly to a candidate state]. Regarding claim 5, Lenovo teaches the connection complies with the high-speed peripheral component interconnect express standard [Page 1, Symptom; PCIe is a high-speed peripheral component interconnect express standard]. Claims 6 – 7 and 10 are system claims corresponding to claims 1 – 2 and are rejected using the same prior art and similar reasoning. The prior art teaches the data storage system [Lenovo, Page 2, Applicable Systems; Choi, Fig 1]. Claim(s) 3 – 4 and 8 - 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lenovo (NVMe SSD transmission mode dynamically changes with AMD new PSPP (PCIE Speed Power Policy) design) referred to as Lenovo in view of Choi (Pub. No.: US 2023/0359399) referred to as Choi as applied to claims 1 and 6 above, and further in view of Wyatt (Pub. No.: US 2007/0140030) referred to as Wyatt. Regarding claim 3, Choi teaches the step of setting the link state adopted by the connection to one of the plurality of candidate link states according to the temperature [Paragraph 0137; The speed is a link state between the host and the memory device and is changed based on a temperature reading. The ability to change it shows the link state is set to one of a plurality of possible states] comprises: setting the link state adopted by the connection to a first link state among the plurality of candidate link states [Paragraph 0137; The speed is a link state between the host and the memory device and is changed based on a temperature reading]; when the connection adopts the first link state, determining whether the temperature is higher than a first temperature upper limit corresponding to the first link state [S920, Fig 9; Paragraphs 0012, 0018, 0137, 0164 – 0191; The temperature is detected as exceeding a temperature threshold when in a current state] in response to the temperature being higher than the first temperature upper limit corresponding to the first link state, setting the link state adopted by the connection to a second link state among the plurality of candidate link states [Paragraphs 0012, 0018, 0137, 0164 – 0191; When the temperature exceeds a temperature threshold the connection speed is reduced which is a second link state different from the link state speed it switched from]. However, Lenovo in view of Choi may not specifically disclose the limitations of when the connection adopts the first link state, determining whether the temperature is higher than a first temperature upper limit corresponding to the first link state or lower than a first temperature lower limit corresponding to the first link state and in response to the temperature being lower than the first temperature lower limit corresponding to the first link state, setting the link state adopted by the connection to a third link state among the plurality of candidate link states. Wyatt discloses when the connection adopts the first link state, determining whether the temperature is higher than a first temperature upper limit corresponding to the first link state or lower than a first temperature lower limit corresponding to the first link state and in response to the temperature being lower than the first temperature lower limit corresponding to the first link state, setting the link state adopted by the connection to a third link state among the plurality of candidate link states [403, Fig 4; 501 - 502, Fig 5; Paragraph 0068; The access rate effects the link state by limiting how fast the memory can be accessed over a link. The use of multiple thresholds shows the system changing speeds based on high and low thresholds being reached and setting the speed accordingly]. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Wyatt in Lenovo in view of Choi, because it allows for more thresholds to be used to monitor temperature of the memory allowing the memory speed to be managed at a smaller granular level to adapt to more granular temperature fluctuations. Regarding claim 4, Choi teaches changing the communication speed between a host [HOST, Fig 1; HOST, Fig 5; Paragraph 0051 - 0052] and a memory device [100, Fig 1; 10, Figs 5, 8, and 10] based on a detected temperature of the memory [Paragraphs 0012, 0018, 0137, 0164 – 0191]. Wyatt discloses a third transmission speed upper limit corresponding to the third link state is higher than a first transmission speed upper limit corresponding to the first link state, and the first transmission speed upper limit corresponding to the first link state is higher than a second transmission speed upper limit corresponding to the second link state [403, Fig 4; 501 - 502, Fig 5; Paragraph 0068; Any number of temperature thresholds are set up and each is associated with an access rate (speed) of the memory. The speed associated with one threshold is either higher or lower than the speed associated with another threshold dependent on the specific thresholds being compared]. Claims 8 - 9 are system claims corresponding to claims 3 - 4 and are rejected using the same prior art and similar reasoning. The prior art teaches the data storage system [Lenovo, Page 2, Applicable Systems; Choi, Fig 1; Wyatt, Fig 2]. Response to Arguments Applicant's arguments filed 01/12/2026 have been fully considered but they are not persuasive. The applicant argues on pages 8 – 11 that the claims are allowed based on the amendments to the claims which recite the specific link state types that are switched. After careful consideration of the applicant’s arguments the examiner respectfully disagrees. The applicant’s arguments are moot in view of the new grounds of rejection. The amendments have changed the scope of the claims requiring further search and consideration of the prior art. The new grounds of rejection are a result of the further search and consideration of the prior art. The examiner suggests amending the claims to include further details defining the inventive concept from the specification to overcome the cited prior art and further advance prosecution. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER D BIRKHIMER whose telephone number is (571)270-1178. The examiner can normally be reached 8-5 Hoteling. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Charles Rones can be reached at 571-272-4085. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Christopher D Birkhimer/ Primary Examiner, Art Unit 2138
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Prosecution Timeline

Aug 07, 2024
Application Filed
Jun 27, 2025
Non-Final Rejection — §102, §103
Sep 26, 2025
Response Filed
Oct 09, 2025
Final Rejection — §102, §103
Jan 12, 2026
Request for Continued Examination
Jan 24, 2026
Response after Non-Final Action
Jan 30, 2026
Non-Final Rejection — §102, §103 (current)

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Prosecution Projections

3-4
Expected OA Rounds
75%
Grant Probability
82%
With Interview (+7.8%)
2y 11m
Median Time to Grant
High
PTA Risk
Based on 496 resolved cases by this examiner. Grant probability derived from career allow rate.

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