Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, 6-8 and 10 are rejected under 35 U.S.C. 102 (a)(1) and (a)(2) as being clearly anticipated by Huai et al. (US 2022/0092462 A) hereinafter referred to as Huai.
Regarding Claim 1, Huai teaches a quantum chip (fig. 3, quantum chip 30), comprising a first substrate and a second substrate (fig. 3, bottom sheet 10 and topsheet 20) arranged oppositely, wherein a reading cavity (figure 3, reading cavity 11) is formed on a side surface of the first substrate facing the second substrate, a quantum bit (fig. 3, qubit array 21) corresponding to the reading cavity is disposed on a side surface of the second substrate facing the first substrate, and the reading cavity and the quantum bit are mutually coupled by forming a capacitor therebetween ([0047], lines 1-4.)
Regarding Claim 2, Huai teaches the quantum chip according to claim 1, wherein a plurality of quantum bits (fig. 3, qubit array 21) are disposed on a surface of the second substrate, the plurality of quantum bits are distributed in an array, and a coupler ([0046], lines 11-14) is disposed between adjacent two of the quantum bits.
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(Huai et al. Page 3, figure 3, quantum chip 30.)
Regarding Claim 3, Huai teaches the quantum chip according to claim 2, wherein the coupler and the quantum bits are both disposed on the side surface of the second substrate facing the first substrate ([0046], lines 11-14.)
Regarding Claim 6, Huai teaches the quantum chip according to claim 1, further comprising a quantum bit driving line (fig. 3, bit control line 12.), wherein the quantum bit driving line and the reading cavity are both disposed on the side surface of the first substrate facing the second substrate (fig. 3, quantum chip 30.) ; and the quantum bit driving line is coupled to an input terminal corresponding to the quantum bit (fig. 3, bit control line 12.)
Regarding Claim 7, Huai teaches the quantum chip according to claim 6, wherein the quantum bit driving line is a driving line that simultaneously transmits a direct current signal and a microwave signal ([0057], lines 1-13).
Regarding Claim 8, Huai teaches the quantum chip according to claim 1, wherein the first substrate (fig. 3, backsheet 10.) is bonded to the second substrate (fig. 3, topsheet 20.), and a gap ([0066], lines 1-3). is formed between the reading cavity and the quantum bit.
Regarding Claim 10, Huai teaches A quantum computing device, comprising the quantum chip according to claim 1 ([0004], line 1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Huai in view of Neill et al. (CA 3090429 A1) hereinafter referred to as Neill.
Regarding Claim 4, as best understood, Huai does not explicitly teach a coupler driving line, wherein the coupler driving line and the reading cavity are both disposed on the side surface of the first substrate facing the second substrate; and the coupler driving line is coupled to the corresponding coupler.
Neil teaches a coupler driving line (fig. 4B, coupler control line 432), wherein the coupler driving line and the reading cavity (fig. 4B, capacitive coupling elements 448) are both disposed on the side surface of the first substrate (fig. 4B, second substrate 422) facing the second substrate (fig. 4B, first substrate 402); and the coupler driving line is coupled to the corresponding coupler.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device described in Huai such that the coupler driving line and the reading cavity are both disposed on the side surface of the first substrate facing the second substrate; and the coupler driving line is coupled to the corresponding coupler, as described in Neill. Doing so allows for improved levels of performance, e.g., improved algorithm execution speed and reduced loss, and perform quantum computations with increased accuracy and reliability (page 3, lines 16-20.)
Regarding Claim 5, Huai as modified by Neill discloses the device of claim 4 as discussed above. Huai further teaches the coupler is a capacitive coupler ([0047], lines 1-4) or an inductive coupler ([0058], lines 5-7; [0070], lines 1-4).
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(fig. 4B)
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Huai in view of Shaw et al. (WO 2018169579 A1) hereinafter referred to as Shaw.
Regarding Claim 9, as best understood, Huai does not explicitly teach the quantum bit is an Xmon quantum bit, and a transverse edge of the Xmon quantum bit overlaps with at least part of a waveguide line predisposed in the reading cavity.
Shaw teaches the quantum chip according to claim 1, wherein the quantum bit is an Xmon quantum bit (figure 2, superconducting qubit 206; [0047], lines 1-4.), and a transverse edge of the Xmon quantum bit overlaps with at least part of a waveguide line ([0049], line 1, readout resonators; fig. 2, readout device 208) predisposed in the reading cavity.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device described in Huai such that the quantum chip according to claim 1, wherein the quantum bit is an Xmon quantum bit, and a transverse edge of the Xmon quantum bit overlaps with at least part of a waveguide line predisposed in the reading cavity, as described in Shaw. Doing so allows for accommodating wiring elements on a separate chip ([0046], lines 1-2) as to accommodate for the decreased wiring space due to the increased number of qubits ([0045], lines 5-6).
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Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TYLER CHRISTIAN GROVER whose telephone number is (571)272-1987. The examiner can normally be reached Monday through Thursday 10:00 am - 8:00 pm.
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/T.C.G./Examiner, Art Unit 2897 09/21/2026
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
