Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Improper Amendment
The amendment filed 08/07/2024 proposes amendments to claim 2 that do not comply with 37 CFR 1.173(b), which sets forth the manner of making amendments in reissue applications. Any omitted matter should be enclosed in brackets [ ] to show deletion (see MPEP §1453).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 7-9, 13-16 and 20-23 are rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki et al. (US 20150221775) in view of Lee (US 20160372497).
Regarding claim 1, Yamazaki (e.g. figs. 1 and 22A) discloses a display device comprising a substrate 100 [¶0155]; a pixel 5311 on the substrate, the pixel including a first thin film transistor TFT and a second thin film transistor TFT. In this case, pixel 5311 includes a transistor 5319 and transistor 5315 (fig. 22A; ¶¶ 0409-0411). The transistors 5319 control electrical connections between wiring lines SL and a gate transistor 5315 (¶0411). Yamazaki, also, discloses a second TFT including a gate insulating film and a second thin film transistor (TFT) on the substrate, the second TFT including: a gate electrode, a second active layer on the substrate, a source electrode, and a drain electrode contacting a top surface of the second active layer; as illustrated by gate electrode 104a, semiconductor layer 106, and source/drain electrodes 116a and 116b of transistor structure 150 (fig. 1). Moreover, a light emitting device is disclosed electrically connected to the second TFT, wherein one of a source and a drain transistor 5315 is connected to an anode of light-emitting element 5314 (¶0411; fig. 22A), and current thought transistor 5315 is supplied to light emitting elements 5314 (¶¶ 0420-0422).
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Yamazaki does not expressly disclose that the first TFT includes a first active layer formed of oxide semiconductor and that the second TFT includes a second active layer formed of polycrystalline silicon. However, Lee teaches that an oxide-semiconductor TFT may be used as a switching TFT because of its low off-current, and the polycrystalline-silicon may be used as a driving TFT of an OLED because of its high mobility and increased current-driving capability (¶¶ 0031; 0137).
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the TFT arrangement of Yamazaki such that the first TFT includes a first active layer formed of oxide semiconductor and the second TFT electrically connected to the light-emitting device, includes a second layer formed of polycrystalline silicon as taught by Lee in order to obtain the know low off-current characteristics of an oxide semiconductor switching TFT while providing the high mobility and increased current-driving capability of a polycrystalline-silicon driving TFT.
Regarding claim 3, Yamazaki teaches another gate electrode 104a disposed below the first active layer 106, wherein a bottom surface of the first active layer faces the another gate electrode, and another source electrode 150 and another drain electrode 150 contacting a top surface of the first active layer (see fig. 1; ¶¶0102) .
Regarding claim 7, Yamazaki in view of Lee teaches a data-driving unit and a multiplexer that drives a plurality of data lines on the substrate, and wherein the multiplexer includes a third TFT including a third active layer formed of polycrystalline silicon (see Lee ¶¶ 0012, 0043; 0139).
Regarding claim 8, Yamazaki in view of Lee teaches that the first TFT is a switching TFT of the pixel, and the first TFT further includes another drain electrode electrically connected to the gate electrode, and another source electrode connected to a data line on the substrate. In this case, the transistor 5319 controls the electrical connection between wiring SL and the gate transistor 5315 (see fig. 22a; ¶0411). Therefore, the transistor 5329 corresponds to the claimed switching TFT connected between the data line and the gate of the second TFT.
Regarding claim 9, Yamazaki in view of Lee teaches a gate-driving unit that drives a plurality of gate lines on the substrate, and wherein the gate-driving unit includes a third TFT including a third active layer formed of polycrystalline silicon. Yamazaki discloses a gate-driving unit that drives a plurality of gate lines on the substrate whereas Lee teaches employing polycrystalline TFT in gate-driving circuitry because of their mobility and driving capability.
Regarding claim 13, Yamazaki teaches that a bottom surface of the second active layer faces the gate electrode, as shown by semiconductor layer 106 disposed above and facing the lower gate electrode in the transistor structure of fig. 1.
Regarding claim 14, Yamazaki teaches that the second TFT is a driving TFT that drives the light-emitting device. The transistor 5315 is electrically connected to light-emitting element 5314, a current through transistor 5315 is supplied to light-emitting element 5314 (fig. 22A; ¶¶ 0411,0420-0422)
Regarding claim 15, Yamazaki in view of Lee teaches a first active layer is formed of an oxide semiconductor (see Lee ¶¶0031, 0137).
Regarding claim 16, Yamazaki in view of Lee teaches that the first TFT further includes: another gate electrode on the first active layer, wherein a bottom surface of the another gate electrode faces the first active layer, and another source electrode and another drain electrode contacting a top surface of the first active layer (see fig. 1; ¶¶0102).
Regarding claim 20, Yamazaki in view of Lee teaches a storage capacitor on the substrate, the storage capacitor includes a lower storage electrode and an upper storage electrode disposed on the lower storage electrode. This corresponds to capacitive element 5318/160 (see fig. 22A and the corresponding capacitor structure of fig. 1).
Regarding claim 21, Yamazaki in view of Lee teaches the first interlayer insulation film on the second active layer contacts the second active layer, and wherein the storage capacitor further includes at least a first part of the first interlayer insulation film and at least a second part of a gate insulating film disposed between the lower storage electrode and the upper storage electrode (as illustrate by the capacitor structure with conductors 104b and 116c in fig. 1).
Regarding claim 22, Yamazaki teaches that the first TFT further includes another gate electrode, and wherein the upper storage electrode is in a same layer as the another gate electrode. Yamazaki discloses that the first TFT includes another gate electrode and that the upper storage electrode is in a same layer as the another gate electrode, wherein the respective conductive members are formed the same conductive layer in the disclosed transistor/capacitor structure of fig. 1
Regarding claim 23, Yamazaki teaches that the lower storage electrode is in a same layer as the gate electrode of the second TFT. Yamazaki discloses that the lower storage electrode is in a same layer as the gate electrode of the second TFT, wherein the lower capacitor conductor and the gate conductor of the driving transistor are formed from the same conductive layer, as illustrated in fig. 1.
Allowable Subject Matter
Claims 2, 4-6, 10-12, 17-19, 24-39 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant is reminded of the continuing obligation under 37 CFR 1.178(b), to timely apprise the Office of any prior or concurrent proceeding in which Patent No. 10,692,893 is or was involved. These proceedings would include any trial before the Patent Trial and Appeal Board, interferences, reissues, reexaminations, supplemental examinations, and litigation.
Applicant is further reminded of the continuing obligation under 37 CFR 1.56, to timely apprise the Office of any information which is material to patentability of the claims under consideration in this reissue application.
These obligations rest with each individual associated with the filing and prosecution of this application for reissue. See also MPEP §§ 1404, 1442.01 and 1442.04.
Applicant is notified that any subsequent amendment to the specification and/or claims must comply with 37 CFR 1.173(b). In addition, for reissue applications filed before September 16, 2012, when any substantive amendment is filed in the reissue application, which amendment otherwise places the reissue application in condition for allowance, a supplemental oath/declaration will be required. See MPEP § 1414.01.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Suzawa and Tsunoda teaches embodiments related to the instant invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LEONARDO ANDUJAR whose telephone number is (571)272-1912. The examiner can normally be reached Monday to Thursday 10 AM to 8 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Patricia L Engle can be reached at (571)272-6660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Leonardo Andujar/
Primary Examiner, Art Unit 3991
Conferees:
/Lee Sanderson/ /Patricia L Engle/
Primary Examiner, Art Unit 3991 SPRS, Art Unit 3991
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