DETAILED ACTION
This Office Action, based on application 18/796,749 filed 7 August 2024, is filed in response to applicant’s amendment and remarks filed 15 October 2025. Claims 1, 4-9, 12-17, 19, and 20 are currently pending and have been fully considered below.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s remarks, filed 15 October 2025 in response to the Office Action mailed 16 July 2025, have been fully considered below.
Specification Objection
The Office withdraws the previously issued objection in response to applicant’s amendment and remarks.
Claim Rejections under 35 U.S.C. § 112
The Office withdraws the previously issued objection in response to applicant’s amendment and remarks.
Claim Rejections under 35 U.S.C. § 101
The applicant traverses the patent eligible subject matter rejection noting the claims have been revised to clarify direction to (a) the opening and closing of certain memory blocks, and (b) the generation of indicators. The applicant further alleges a human cannot open or close memory blocks of a semiconductor nor store/update metadata; thus the claims are not directed to an abstract idea without significantly more. The Office maintains a rejection to the claims for reasons now presented below responsive to applicant’s amendment. While the applicant asserts a human cannot open/close memory blocks nor store/update metadata in memory blocks (and thus the claims add ‘additional elements’ for consideration under Step 2A Prong 2 and Step 2B), the Office asserts the additional elements fail to integrate the noted abstract idea into a practical application and are not sufficient to amount to significantly more than the abstract idea for reasons presented in the rejection of record. While the applicant alleges a human cannot open/close memory blocks, the Office notes the specification (and most notably the claims) does not appear to specify nor is claim-limited as to how memory blocks are opened/closed. The Office asserts the act of opening/closing a memory block may simply be flipping a bit flag stored somewhere, updating a value in a table, or making some other judgement regarding a status of the block to which the Office asserts the concept, other than being claimed as being performed in memory, may be performed mentally or simply with pencil/paper and thus is an abstract idea. The Office reminds the applicant that a claim that requires a computer may still recite a mental process (see MPEP § 2160.04(a)(2)(III)(C).
Claim Rejections under 35 U.S.C. § 102/103
The applicant traverses the prior art rejection to the independent claims alleging cited prior art fails to disclose the features of the independent claims as now presented. Specifically, the applicant alleges cited prior art fails to disclose the claimed indicators “selected from within a set range of values” as now amended since cited prior art instead discloses timestamps. The Office notes the values of the indicators are not limited in the claims as being assigned in a ‘round-robin’ fashion. The Office asserts FISHER’s timestamp meets the broadest reasonable interpretation of a value within a set range of values (e.g. one may readily recognize “12:00” as a timestamp while not recognize “qw3e0r9” or some other random string; thus, a value of timestamp may be said to be within a set range as only certain strings may be recognized as timestamps). While applicant’s indicators are not limited in the claims as values being assigned in a round-robin fashion, the Office asserts the claims would be, at a minimum, rendered obvious when timestamps are represented by a value read from a wall clock (e.g. with values between 1:00 and 12:59).
On Pages 11-14, the applicant further traverses the prior art rejection issued in further view of CHOI to dependent claims where some of the features of the dependent claims have been incorporated into the amended independent claim. The applicant further alleges FISHER’s and CHOI’s timestamps are not analogous to applicant’s claimed indicators since prior art teaches timestamps assigned to blocks being erased while applicant’s claimed block erase indicator is assigned to “the memory block being closed” (or as claimed, “assign the value … to a block erase indicator associated with a memory block to be closed”). The Office asserts the timestamp indicates when a block is erased and submits the block may only be considered to be erased (or closed) after the timestamp thus meeting the scope of the limitation. The applicant further alleges CHOI fails to disclose the enabling of the erase interval management mode since “the number of available memory blocks in the present invention is different from the number of erase blocks or the assignment interval between successive assignments of erase blocks to free blocks disclosed in CHOI”. As noted by the applicant, CHOI discloses adjusting the number of erase blocks according to the assignment interval. The Office asserts the adjustment of the number of erase blocks in CHOI includes managing the number of erase blocks to a set value (e.g. ¶[0056]) that includes erasing invalid blocks to become new erase blocks if the number of erase blocks is less than the set value. Since FISHER discloses timestamps assigned to blocks when erasing the block and CHOI discloses adjusting the number of memory blocks including adding new erase blocks when the existing number of erase blocks is less than a set value, the Office asserts cited prior art teaches indicator management when the number of available memory blocks is below a threshold meeting the claim.
Claim Objections
The following claims are objected to due to informalities:
Claims 1, 9, and 17: While the Office is not rejecting the following limitation as being indefinite, the Office asserts the limitation may be improved grammatically:
“open the closed memory block selected to process a write request when comparing a difference between a value of the preliminary erase indicator set to the new value and a value of the block erase indicator of the closed memory block selected to process the write request and a result of the comparison exceeds a set threshold”
While one may compare two ‘things’, the element or property of the two ‘things’ should be specified. One can compare the difference between two cars, but the two cars may be compared in different ways including price tag and color; likewise, one may compare two indicators, but the claim doesn’t mention what is being compared which may include memory address, storage location, size, or in this case, value stored. Furthermore, the trigger or event that causes the memory block to be opened should be clarified. The Office will withdraw the objection after applicant’s consideration.
Claims 5, 13, and 19: Lack of clear antecedent basis of the term “the opened selected memory block”. The Office strongly discourages using adjectives of the claim term to describe a particular state of an item. For example, “a memory block to be closed” (e.g. parent Claim 1), “the closed memory block” (e.g. parent Claim 1), and “the opened selected memory block” (e.g. Claim 5) all refer to the same memory block.
Claims 5, 13, and 19: The claim is directed to the term “a set threshold”. Each respective parent claim is also directed to “a set threshold”. The claims are unclear as to whether or not the threshold are the same or different. If they’re the same, Claims 5, 13, and 19 should be directed to ‘the set threshold’; if different, Claims 5, 13, and 19 should be directed to ‘a second set threshold’ (or use some other adjective to distinguish the thresholds). Furthermore, the claims are directed to “an interval … exceeds a set threshold” while respective parent claims are directed to “a difference … exceeds the set threshold”. Is “a difference” the same as “an interval”? If not, then what is the distinction?
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 4-9, 12-17, 19, and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The independent claims (e.g. Claim 1) recite the limitation "the closed memory block". There is insufficient antecedent basis for this limitation in the claim. While the independent claims are limited to “a memory block to be closed”, the claims do not expressly establish any “closed memory block”. Furthermore, regarding the limitation “open the closed memory block selected to process a write request”, the claim does not provide any antecedent basis for selection of a memory block with the intended use of the selection to process a write request.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1, 4-9, 12-17, 19, and 20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception without significantly more. Patent Eligibility is determined as set forth under the 2019 Patent Eligibility Guidelines (see MPEP § 2106). The analysis of the claims in view of the guidelines are presented below.
Claim 1:
Regarding Step 1, the claim is directed to a controller (e.g. a machine/manufacture). Thus, the claim is directed to one of the four categories of invention.
Regarding Step 2A Prong 1, this part of the eligibility analysis evaluates whether the claim recites a judicial exception. The claim includes the following limitations:
A memory controller configured to control a storage medium including a plurality of memory blocks, the memory controller comprising at least one processor,
wherein the at least one processor is configured to enable an erase interval management mode when a number of available memory blocks in the plurality of memory blocks is below a predetermined threshold, and wherein when the erase interval management mode is enabled, the at least one processor is configured to:
generate a preliminary erase indicator with a value from a set range of values,
assign the value of the preliminary erase indicator to a block erase indicator associated with a memory block to be closed,
update the preliminary erase indicator with a new value, and
open the closed memory block selected to process a write request when a difference between the preliminary erase indicator set to the new value and the block erase indicator of the closed memory block selected to process the write request exceeds a set threshold.
The Office submits the underlined portions above recite a judicial exception.
Limitations (2) through (6) are effectively directed to a sequence of steps (or algorithm) of comparing two random numbers for the intended use of determining whether to perform a task. The broadest reasonable interpretation of Limitations (2) through (5) may be summarized as follows:
Limitation (3)’s “generates …” limitation is analogous to a first person performing the task of “Picking a number between 1 and 10 …”;
Limitation (4)’s “assigns …” limitation is analogous to associating the number picked in Limitation (3) to a second person.
Limitation (5)’s “update …” limitation is analogous to the first person performing the task of “Pick another number between 1 and 10 …”
Limitation (6)’s “when a difference … exceeds a set threshold” limitation is analogous to comparing the first person and the second person’s numbers to a threshold number. As a result of performing the comparison, the claim is further directed to “open the closed block selected to process a write request”. The Office asserts the act of ‘open{ing} the closed memory block’ may be simply performing a judgement on the status of the block. The Office further asserts that while ‘the closed memory block’ may be “selected to process a write request”, the Office maintains the limitation is indefinite for reasons presented in the 112(b) rejection and further asserts the limitation is merely an intended use recitation and any processing of the write request is not required by the claim.
Limitation (2) “enabling an erase interval management mode” limitation is analogous to evaluating a condition (number of available blocks) that is then used to determine when to perform (a) through (d);
Enumerated groupings of abstract ideas include “Mental Processes” (MPEP 2106.04(a)). The Office has determined that the underlined portions of the limitations above fall within the “Mental Processes” grouping as the limitations can practically be performed in the human mind, including for example, observations, evaluations, judgements, and opinions (MPEP 2106.04(a)(2)(III)).
The Office has determined the claim recites a judicial exception requiring further analysis in Prong 2.
Regarding Step 2A Prong 2, this part of the eligibility analysis evaluates whether the claim as a whole integrates the recited judicial exception into a practical application of the exception. This evaluation is performed by (a) identifying whether there are any additional elements recited in the claim beyond the judicial exception, and (b) evaluating those additional elements individually and in combination to determine whether the claim as a whole integrates the exception into a practical application. Besides the abstract idea of the claim, the claim further recites the following additional elements:
A memory controller configured to control a storage medium including a plurality of memory blocks, the memory controller comprising at least one processor,
wherein the at least one processor is configured to enable an erase interval management mode when a number of available memory blocks in the plurality of memory blocks is below a predetermined threshold, and wherein when the erase interval management mode is enabled, the at least one processor is configured to:
generate a preliminary erase indicator with a value from a set range of values,
assign the value of the preliminary erase indicator to a block erase indicator associated with a memory block to be closed,
update the preliminary erase indicator with a new value, and
open the closed memory block selected to process a write request when a difference between the preliminary erase indicator set to the new value and the block erase indicator of the closed memory block selected to process the write request exceeds a set threshold.
Limitations (1), (2), (4), and (6) recite additional elements that include a controller’s ‘at least one processor’ with the purpose of the controller to ‘control’ or operate on storage that includes memory blocks. While the claim recites the controller is configured to ‘control’, the claim is not further limited to performing any actions on a memory block. The Office submits the claimed memory controller with at least one processor and associated storage medium is recited at a high level of generality such that the claim amounts to no more than mere instructions to apply the identified abstract idea using a generic computer. Accordingly, the additional elements do not integrate the abstract idea into a practical application because the controller does not impose any meaningful limits on practicing the abstract idea (MPEP 2106.05(f)).
Thus, the Office has determined that the noted additional elements fail to integrate the recited judicial exception into a practical application requiring further analysis in Step 2B.
Regarding Step 2B, this part of the eligibility analysis evaluates the additional elements of the claim to determine whether they amount to an inventive concept. As noted in the analysis of Step 2A Prong 2, the Office has determined those additional elements.
Regarding Limitations (1), (2), (4), and (6), the claimed memory controller with at least one processor and associated storage medium, again, is recited at a high level of generality such that the claim amounts to no more than mere instructions to apply the identified abstract idea using a generic computer (MPEP 2106.05(f)).
As such, the claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception and thus is not patent eligible.
Claim 9:
The claim recites the following limitations:
A storage apparatus comprising: a storage medium including a plurality of memory blocks; and a memory controller controlling the storage medium and including at least one processor, wherein the at least one processor is configured to:
enable an erase interval management mode when a number of available memory blocks is below a predetermined threshold,
generate a preliminary erase indicator with a value in a set range when the erase interval management mode is enabled,
assign the value of the preliminary erase indicator to a block erase indicator associated with a memory block to be closed, and
update the preliminary erase indicator with a new value, and
open the closed memory block selected to process a write request by comparing the block erase indicator of the closed memory block selected to process the write request and the preliminary erase indicator set to the new value.
Similar to the analysis of Claim 1 above:
The claim is directed to an apparatus (or machine/manufacture); thus, the claim is directed to one of the four categories of invention.
The underlined limitations above recite a judicial exception
Limitations (1), (4), and (6) recite additional elements that fail to integrate the recited judicial exception into a practical application
Limitations (1), (4), and (6) do not include additional elements that are sufficient to amount to significantly more than the judicial exception
Claim 17:
The claim recites the following limitations:
A method of operating a memory controller, the memory controller including at least one processor that controls a storage medium including a plurality of memory blocks, the method comprising:
enabling, by the at least one processor, an erase interval management mode when the number of available memory blocks is below a predetermined threshold;
generating, by the at least one processor, a preliminary erase indicator with a value within a set range of values when the erase interval management mode is enabled;
assigning, by the at least one processor, the value of the preliminary erase indicator to a block erase indicator associated with a memory block to be closed and
updating the preliminary erase indicator with a new value; and
opening a closed memory block for processing a write request when a difference between the block erase indicator of the closed memory block selected to process the write request and the preliminary erase indicator set to the new value exceeds a set threshold
Similar to the analysis of Claim 1 above:
The claim is directed to a method (or process); thus, the claim is directed to one of the four categories of invention.
The underlined limitations above recite a judicial exception
Limitations (1) through (6) recite additional elements that fail to integrate the recited judicial exception into a practical application
Limitations (1) through (6) do not include additional elements that are sufficient to amount to significantly more than the judicial exception
Since “enabling an erase interval management mode” is contingent on “when the number of available memory blocks is below a predetermined threshold” and the contingency is not required (e.g. the claim does not require the number of available memory blocks to ever fall below any threshold), the broadest reasonable interpretation of the claim does not require the step of ‘enabling …’ to be performed by the method. Furthermore, “opening a closed memory block for processing a write request …” is contingent on “when a difference … exceeds a set threshold” and again the contingency is not required thus the step of ‘opening …’ is not required to be performed by the method. See EXAMINER’S NOTE below.
Claims 4 and 12:
Claim 4 recites the following limitation beyond that recited in parent Claim 1:
wherein the at least one processor generates a digital code corresponding to a natural number within the set range of values as the preliminary erase indicator
The limitation is directed to further defining a type of value that is generated during the generation of the erase indicator. Thus, the limitation further expands upon the abstract idea of comparing two random numbers for the intended use of determining whether to perform a task. Again, the Office further notes that the sequence of steps only results in the “determining” of whether or not the task to “open” a block is performed; the claim does not require the actual performance of the task. Enumerated groupings of abstract ideas include “Mental Processes” (MPEP 2106.04(a)). The Office has determined that the underlined portions of the limitations above fall within the “Mental Processes” grouping as the limitations can practically be performed in the human mind, including for example, observations, evaluations, judgements, and opinions (MPEP 2106.04(a)(2)(III)). The Office has determined the claim also comprises additional elements requiring further analysis under Step 2A Prong 2 and Step 2B.
While Claim 4 further recites an additional element of “the at least one processor” performing the erase indicator generation, the Office maintains the additional element fails to integrate the recited judicial exception into a practical application and the additional element is not sufficient to amount to significantly more than the judicial exception for reasons similarly recited with respect to Claim 1’s analysis regarding applying the identified abstract idea using a generic computer (MPEP 2106.05(f)).
Claim 12 recites an additional limitation beyond that recited in parent Claim 9 and similar to the additional limitation recited in Claim 4. Claim 12 has been determined not to be patent eligible for reasons similarly recited in regards to the analysis performed for parent Claim 9 and related Claim 4.
Claims 5, 13, and 19:
Claim 5 recites the following limitation beyond that recited in parent Claim 4:
wherein the at least one processor erases the opened selected memory block when an interval between the block erase indicator of the selected memory block and the preliminary erase indicator exceeds a set threshold
The limitation is not found to further the “Mental Process” identified in parent Claim 1; however, Claim 5 is further directed to a judicial exception due to the identified “Mental Process” of Claim 1. The Office has determined the claim also comprises additional elements requiring further analysis under Step 2A Prong 2 and Step 2B.
While Claim 5 recites additional elements of erasing a block under the condition that a comparison between indicators exceeds a threshold, the Office notes the limitation has nothing to do with the identified abstract idea of comparing two random numbers for the intended use of determining whether to perform a task of determining whether to process a write request. As such, the additional element merely specifies an insignificant extra-solution activity to the recited judicial exception since the limitation fails to integrate the judicial exception into a practical application to show any improvement in the functioning of a computer. Thus, at most, the additional limitation recites a form of mere data gathering (MPEP 2106.05(g)). Furthermore, the courts have recognized, similar to the additional element, that computer functions including “storing and retrieving information in memory” to be well-understood, routine, and conventional functions when they are claimed in a merely generic manner or as insignificant extra-solution activity (MPEP 2106.05(d)(II)). While Claim 7 further recites additional elements of “the at least one processor” performing the erasing function, the Office maintains the additional elements fail to integrate the recited judicial exception into a practical application and the additional elements are not sufficient to amount to significantly more than the judicial exception for reasons similarly recited with respect to Claim 1’s analysis regarding applying the identified abstract idea using a generic computer (MPEP 2106.05(f)).
Claims 13 and 19 recite an additional limitation beyond that recited in parent Claims 12 and 17, respectively, and similar to the additional limitation recited in Claim 5. Claims 13 and 19 have been determined not to be patent eligible for reasons similarly recited in regards to the analysis performed for parent Claims 12 and 17, respectively, and related Claim 5. See EXAMINER’S NOTE below regarding the broadest reasonable interpretation of method Claim 19.
Claims 6 and 14:
Claim 6 recites the following limitation beyond that recited in parent Claim 1:
wherein the at least one processor controls the block erase indicator to be included in metadata of the memory block to be closed
The limitation is directed to associating or characterizing the erase indicator as ‘metadata’. The claim fails to recite where any ‘metadata’ for the memory block exists or what, if any, other data qualifies as ‘metadata’ for the memory block. As such, the limitation may simply serve as a classification of the assigned erase indicator as being ‘metadata’ similar to an observation of the data. Thus, the limitation further expands upon the abstract idea of comparing two random numbers for the intended use of determining whether to perform a task. Enumerated groupings of abstract ideas include “Mental Processes” (MPEP 2106.04(a)). The Office has determined that the underlined portions of the limitations above fall within the “Mental Processes” grouping as the limitations can practically be performed in the human mind, including for example, observations, evaluations, judgements, and opinions (MPEP 2106.04(a)(2)(III)). The Office has determined the claim also comprises additional elements requiring further analysis under Step 2A Prong 2 and Step 2B.
While Claim 6 further recites additional elements of “the at least one processor” performing the controlling with the controlling being performed on data associated with ‘memory’ blocks, the Office maintains the additional elements fail to integrate the recited judicial exception into a practical application and the additional elements are not sufficient to amount to significantly more than the judicial exception for reasons similarly recited with respect to Claim 1’s analysis regarding applying the identified abstract idea using a generic computer (MPEP 2106.05(f)).
Claim 14 recites an additional limitation beyond that recited in parent Claim 9 and similar to the additional limitation recited in Claim 6. Claim 14 has been determined not to be patent eligible for reasons similarly recited in regards to the analysis performed for parent Claim 9 and related Claim 6.
Claims 7, 15, and 20:
Claim 7 recites the following limitation beyond that recited in parent Claim 1:
when the memory block to be closed includes an empty storage space, the at least one processor writes data of a pattern corresponding to the block erase indicator to the empty storage space
The limitation is not found to further the “Mental Process” identified in parent Claim 1; however, Claim 7 is further directed to a judicial exception due to the identified “Mental Process” of Claim 1. The Office has determined the claim also comprises additional elements requiring further analysis under Step 2A Prong 2 and Step 2B.
While Claim 7 recites additional elements of writing data of a pattern to empty storage space under the condition that the memory block is “to be closed”, the Office notes the limitation has nothing to do with the identified abstract idea of comparing two random numbers for the intended use of determining whether to perform a task of determining whether to process a write request. As such, the additional element merely specifies an insignificant extra-solution activity to the recited judicial exception since the limitation fails to integrate the judicial exception into a practical application to show any improvement in the functioning of a computer. Thus, at most, the additional limitation recites a form of mere data gathering (MPEP 2106.05(g)). Furthermore, the courts have recognized, similar to the additional element, that computer functions including “storing and retrieving information in memory” to be well-understood, routine, and conventional functions when they are claimed in a merely generic manner or as insignificant extra-solution activity (MPEP 2106.05(d)(II)). While Claim 7 further recites additional elements of “the at least one processor” performing the writing of a pattern to empty storage space of ‘memory’ blocks, the Office maintains the additional elements fail to integrate the recited judicial exception into a practical application and the additional elements are not sufficient to amount to significantly more than the judicial exception for reasons similarly recited with respect to Claim 1’s analysis regarding applying the identified abstract idea using a generic computer (MPEP 2106.05(f)).
Claims 15 and 20 recite an additional limitation beyond that recited in parent Claims 9 and 17, respectively, and similar to the additional limitation recited in Claim 7. Claims 15 and 20 have been determined not to be patent eligible for reasons similarly recited in regards to the analysis performed for parent Claims 9 and 17, respectively, and related Claim 7. See EXAMINER’S NOTE below regarding the broadest reasonable interpretation of method Claim 20
Claims 8 and 16:
Claim 8 recites the following limitation beyond that recited in parent Claim 1:
the at least one processor writes data in a pattern corresponding to the block erase indicator to a free storage space of a memory block being recovered when a recovery operation in response to a sudden power off (SPO) is operated
The limitation is not found to further the “Mental Process” identified in parent Claim 1; however, Claim 7 is further directed to a judicial exception due to the identified “Mental Process” of Claim 1. The Office has determined the claim also comprises additional elements requiring further analysis under Step 2A Prong 2 and Step 2B.
While Claim 8 recites additional elements of writing data of a pattern in response to a computer system experiencing power loss, the Office notes the limitation has nothing to do with the identified abstract idea of comparing two random numbers for the intended use of determining whether to perform a task of determining whether to process a write request. As such, the additional element merely specifies an insignificant extra-solution activity to the recited judicial exception since the limitation fails to integrate the judicial exception into a practical application to show any improvement in the functioning of a computer. Thus, at most, the additional limitation recites a form of mere data gathering (MPEP 2106.05(g)). Furthermore, the courts have recognized, similar to the additional element, that computer functions including “storing and retrieving information in memory” to be well-understood, routine, and conventional functions when they are claimed in a merely generic manner or as insignificant extra-solution activity (MPEP 2106.05(d)(II)). While Claim 8 further recites additional elements of “the at least one processor” performing the writing of a pattern to free storage space of ‘memory’ blocks, the Office maintains the additional elements fail to integrate the recited judicial exception into a practical application and the additional elements are not sufficient to amount to significantly more than the judicial exception for reasons similarly recited with respect to Claim 1’s analysis regarding applying the identified abstract idea using a generic computer (MPEP 2106.05(f)).
Claim 16 recites an additional limitation beyond that recited in parent Claim 9 and similar to the additional limitation recited in Claim 8. Claim 16 has been determined not to be patent eligible for reasons similarly recited in regards to the analysis performed for parent Claim 9 and related Claim 8.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1, 4-6, 9, 12-14, 17, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over FISHER (US PGPub 2015/0161034) in further view of CHOI et al (US PGPub 2015/0277795).
With respect to Claim 1, FISHER discloses a memory controller (Fig 1, Flash Controller 124 and CPU 128) configured to control a storage medium including a plurality of memory blocks (Fig 1, NAND flash memory array 140),
the memory controller comprising at least one processor (Fig 1, CPU 128),
wherein the at least one processor is configured to:
generate a preliminary erase indicator with a value from a set range of values (¶[0045] – “Each entry 1000 preferably further includes an erase timestamp 1004 indicating an erase time of the block identified by the PBA 1002”; ¶[0046] – a ‘current time’),
assign the value of the preliminary erase indicator to a block erase indicator to associated with a memory block to be closed (¶[0045] – “Each entry 1000 preferably further includes an erase timestamp 1004 indicating an erase time of the block identified by the PBA 1002”),
update the preliminary erase indicator with a new value (¶[0046] – a ‘current time’), and
open the closed block selected to process a write request when a difference between the preliminary erase indicator set to the new value and the block erase indicator of the closed memory block selected to process the write request exceeds a set threshold (¶]0046] – “At block 904, flash controller 124 calculates the current dwell time of the block identified by the selected entry 1000, for example, by computing a difference between a current time (or in alternative embodiments, the time of a previous erasure or programming of the page) and the erase timestamp 1044 specified by the selected entry 1000. At block 906, flash controller 124 determines whether or not a dwell time threshold for the block has been satisfied (e.g. whether the dwell time computed at block 904 is equal to and/or greater than the dwell time threshold)”; ¶[0047] and ¶[0048] discuss what happens if the threshold is or is not satisfied including “In response to a determination that the dwell time threshold of the block has been satisfied, flash controller 124 transfers at least the PBA 1002 from the selected entry 1000 in EBL 152 to an entry of an available block queue (ABQ) 154 to make the block available for programming and frees the selected entry 1000 in EBL 152 (block 908)”).
FISHER may not explicitly disclose wherein the at least one processor is configured to enable an erase interval management mode when a number of available memory blocks in the plurality of memory blocks is below a predetermined threshold and wherein when the erase interval management mode is enabled, perform the generation, the assignment, and the update.
However, CHOI discloses wherein the at least one processor is configured to enable an erase interval management mode when a number of available memory blocks in the plurality of memory blocks is below a predetermined threshold and wherein when the erase interval management mode is enabled, perform the generation, the assignment, and the update (Fig 14; ¶[0107-0108] – an assignment interval calculator calculates the assignment interval, and adjusts the number of memory blocks, maintained as erase blocks, according to the assignment interval; “In step S620, the set number of erase blocks is adjusted … the set number may be adjusted according to a method described with reference to Figs 3 to 6”; ¶[0056] – “If the number of erase blocks of the reserved block queue 121 is less than a set number, then the erase manager 127 erases an invalid block(s) to increase the number of erase blocks.”).
FISHER and CHOI are analogous art because they are from the same field of endeavor of management of memory blocks. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of FISHER and CHOI before him or her, to modify the enabling of the garbage collection process of FISHER to be based on an assignment interview of free blocks as taught by CHOI. A motivation for doing so would have been to produce erase blocks before a free block is requested so that the free block may be instantly assigned without performing an erase operation when a free block is requested thus speeding up the memory system (¶[0026]). Therefore, it would have been obvious to combine FISHER and CHOI to obtain the invention as specified in the instant claims.
With respect to Claim 9, FISHER discloses a storage apparatus comprising:
a storage medium including a plurality of memory blocks (Fig 1, NAND flash memory array 140); and
a memory controller (Fig 1, Flash Controller 124 and CPU 128) controlling the storage medium and including at least one processor (Fig 1, CPU 128),
wherein the at least one processor is configured to:
generate a preliminary erase indicator with a value in a set range (¶[0045] – “Each entry 1000 preferably further includes an erase timestamp 1004 indicating an erase time of the block identified by the PBA 1002”; ¶[0046] – a ‘current time’),
assign the value of the preliminary erase indicator to a block erase indicator associated with a memory block to be closed (¶[0045] – “Each entry 1000 preferably further includes an erase timestamp 1004 indicating an erase time of the block identified by the PBA 1002”), and
update the preliminary erase indicator with a new value (¶[0046] – a ‘current time’), and
open the closed memory block selected to process a write request by comparing the block erase indicator of the closed memory block selected to process the write request and the preliminary erase indicator set to the new value (¶]0046] – “At block 904, flash controller 124 calculates the current dwell time of the block identified by the selected entry 1000, for example, by computing a difference between a current time (or in alternative embodiments, the time of a previous erasure or programming of the page) and the erase timestamp 1044 specified by the selected entry 1000. At block 906, flash controller 124 determines whether or not a dwell time threshold for the block has been satisfied (e.g. whether the dwell time computed at block 904 is equal to and/or greater than the dwell time threshold)”; ¶[0047] and ¶[0048] discuss what happens if the threshold is or is not satisfied including “In response to a determination that the dwell time threshold of the block has been satisfied, flash controller 124 transfers at least the PBA 1002 from the selected entry 1000 in EBL 152 to an entry of an available block queue (ABQ) 154 to make the block available for programming and frees the selected entry 1000 in EBL 152 (block 908)”).
FISHER may not explicitly disclose wherein the at least one processor is configured to enable an erase interval management mode when a number of available memory blocks is below a predetermined threshold and generate a preliminary erase indicator … when the erase interval management mode is enabled.
However, CHOI discloses wherein the at least one processor is configured to enable an erase interval management mode when a number of available memory blocks is below a predetermined threshold and generate a preliminary erase indicator … when the erase interval management mode is enabled (Fig 14; ¶[0107-0108] – an assignment interval calculator calculates the assignment interval, and adjusts the number of memory blocks, maintained as erase blocks, according to the assignment interval; “In step S620, the set number of erase blocks is adjusted … the set number may be adjusted according to a method described with reference to Figs 3 to 6”; ¶[0056] – “If the number of erase blocks of the reserved block queue 121 is less than a set number, then the erase manager 127 erases an invalid block(s) to increase the number of erase blocks.”).
FISHER and CHOI are analogous art because they are from the same field of endeavor of management of memory blocks. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of FISHER and CHOI before him or her, to modify the enabling of the garbage collection process of FISHER to be based on an assignment interview of free blocks as taught by CHOI. A motivation for doing so would have been to produce erase blocks before a free block is requested so that the free block may be instantly assigned without performing an erase operation when a free block is requested thus speeding up the memory system (¶[0026]). Therefore, it would have been obvious to combine FISHER and CHOI to obtain the invention as specified in the instant claims.
With respect to Claim 17, FISHER discloses a method of operating a memory controller (Fig 1, Flash Controller 124 and CPU 128), the memory controller including at least one processor (Fig 1, CPU 128) that controls a storage medium including a plurality of memory blocks (Fig 1, NAND flash memory array 140), the method comprising:
(¶[0045] – “Each entry 1000 preferably further includes an erase timestamp 1004 indicating an erase time of the block identified by the PBA 1002”; ¶[0046] – a ‘current time’. The step of ‘generating …’ is not required to be performed given the broadest reasonable interpretation of the method since the step is contingent ‘when the erase interval management mode is enabled’ and the contingency is not required by the claim. See EXAMINER’S NOTE below);
assigning, by the at least one processor, the value of the preliminary erase indicator to a block erase indicator associated with a memory block to be closed (¶[0045] – “Each entry 1000 preferably further includes an erase timestamp 1004 indicating an erase time of the block identified by the PBA 1002”) and updating the preliminary erase indicator with a new value (¶[0046] – a ‘current time’); and
(¶]0046] – “At block 904, flash controller 124 calculates the current dwell time of the block identified by the selected entry 1000, for example, by computing a difference between a current time (or in alternative embodiments, the time of a previous erasure or programming of the page) and the erase timestamp 1044 specified by the selected entry 1000. At block 906, flash controller 124 determines whether or not a dwell time threshold for the block has been satisfied (e.g. whether the dwell time computed at block 904 is equal to and/or greater than the dwell time threshold)”; ¶[0047] and ¶[0048] discuss what happens if the threshold is or is not satisfied including “In response to a determination that the dwell time threshold of the block has been satisfied, flash controller 124 transfers at least the PBA 1002 from the selected entry 1000 in EBL 152 to an entry of an available block queue (ABQ) 154 to make the block available for programming and frees the selected entry 1000 in EBL 152 (block 908)”. The step of ‘opening …’ is not required to be performed given the broadest reasonable interpretation of the method since the step is contingent ‘when a difference … exceeds a set threshold’ and the contingency is not required by the claim. See EXAMINER’S NOTE below).
FISHER may not explicitly disclose enabling, by the at least one processor, an erase interval management mode when the number of available memory blocks is below a predetermined threshold and generating, by the at least one processor, a preliminary erase indicator … when the erase interval management mode is enabled.
However, CHOI discloses (Fig 14; ¶[0107-0108] – an assignment interval calculator calculates the assignment interval, and adjusts the number of memory blocks, maintained as erase blocks, according to the assignment interval; “In step S620, the set number of erase blocks is adjusted … the set number may be adjusted according to a method described with reference to Figs 3 to 6”; ¶[0056] – “If the number of erase blocks of the reserved block queue 121 is less than a set number, then the erase manager 127 erases an invalid block(s) to increase the number of erase blocks.”. The steps of ‘enabling …’ and ‘generating …’ are not required to be performed given the broadest reasonable interpretation of the method since the steps are contingent ‘the number of available memory blocks is below a predetermined threshold’ and ‘when the erase interval management mode is enabled’, respectively and the contingencies are not required by the claim. See EXAMINER’S NOTE below).
FISHER and CHOI are analogous art because they are from the same field of endeavor of management of memory blocks. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of FISHER and CHOI before him or her, to modify the enabling of the garbage collection process of FISHER to be based on an assignment interview of free blocks as taught by CHOI. A motivation for doing so would have been to produce erase blocks before a free block is requested so that the free block may be instantly assigned without performing an erase operation when a free block is requested thus speeding up the memory system (¶[0026]). Therefore, it would have been obvious to combine FISHER and CHOI to obtain the invention as specified in the instant claims.
With respect to Claims 4 and 12, the combination of FISHER and CHOI disclose the memory controller/storage apparatus of each respective parent claim.
FISHER further discloses wherein the at least one processor generates a digital code corresponding to a natural number within the set range of values as the preliminary erase indicator (¶[0045] – “Each entry 1000 preferably further includes an erase timestamp 1004 indicating an erase time of the block identified by the PBA 1002”).
With respect to Claims 5, 13, and 19, the combination of FISHER and CHOI disclose the memory controller/storage apparatus/method of each respective parent claim.
FISHER further discloses wherein the at least one processor erases the opened selected memory block when an interval between the block erase indicator of the selected memory block and the preliminary erase indicator exceeds a set threshold (¶]0046] – “At block 904, flash controller 124 calculates the current dwell time of the block identified by the selected entry 1000, for example, by computing a difference between a current time (or in alternative embodiments, the time of a previous erasure or programming of the page) and the erase timestamp 1044 specified by the selected entry 1000. At block 906, flash controller 124 determines whether or not a dwell time threshold for the block has been satisfied (e.g. whether the dwell time computed at block 904 is equal to and/or greater than the dwell time threshold)”; ¶[0047] and ¶[0048] discuss what happens if the threshold is or is not satisfied including “In response to a determination that the dwell time threshold of the block has been satisfied, flash controller 124 transfers at least the PBA 1002 from the selected entry 1000 in EBL 152 to an entry of an available block queue (ABQ) 154 to make the block available for programming and frees the selected entry 1000 in EBL 152 (block 908)”. See EXAMINER’S NOTE below regarding the broadest reasonable interpretation of method Claim 19).
With respect to Claims 6 and 14, the combination of FISHER and CHOI disclose the memory controller/storage apparatus of each respective parent claim.
FISHER further discloses wherein the at least one processor controls the block erase indicator to be included in metadata of the memory block to be closed (¶[0051] – “flash controller 124 additionally determines metadata for the page and stores the metadata in the memory block containing the page, either in the page itself of elsewhere in the memory block … for example, … flash controller 124 calculates and stores dwell time information for the page of physical memory”).
Claim(s) 7, 15, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over FISHER in further view of CHOI and MOON et al (US PGPub 2018/0004653).
With respect to Claims 7, 15, and 20, the combination of FISHER and CHOI disclose the memory controller/storage apparatus/method of each respective parent claim.
FISHER and CHOI may not explicitly disclose when the memory block to be closed includes an empty storage space, the at least one processor writes data of a pattern corresponding to the block erase indicator to the empty storage space.
However, MOON discloses when the memory block to be closed includes an empty storage space, the at least one processor writes data of a pattern corresponding to the block erase indicator to the empty storage space (¶[0092] – a dummy closing operation where a memory block is programmed with dummy data where data is stored may be executed in response to a block meeting a threshold time; See EXAMINER’S NOTE below regarding the broadest reasonable interpretation of method Claim 20).
FISHER, CHOI, and MOON are analogous art because they are from the same field of endeavor of management of memory blocks. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of FISHER, CHOI, and MOON before him or her, to modify a block that hasn’t been erased recently of the combination of FISHER and CHOI to be filled with dummy data as taught by MOON. A motivation for doing so would have been to enable blocks that haven’t been accessed recently to be eligible for victim selection as a target for new data thus making more free blocks eligible for writing. Therefore, it would have been obvious to combine FISHER, CHOI, and MOON to obtain the invention as specified in the instant claims.
Claim(s) 8 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over FISHER in further view of CHOI and KAO et al (US PGPub 2023/0073518).
With respect to Claims 8 and 16, the combination of FISHER and CHOI disclose the memory controller/storage apparatus of each respective parent claim.
FISHER and CHOI may not explicitly disclose the at least one processor writes data in a pattern corresponding to the block erase indicator to a free storage space of a memory block being recovered when a recovery operation in response to a sudden power off (SPO) is operated.
However, KAO discloses the at least one processor writes data in a pattern corresponding to the block erase indicator to a free storage space of a memory block being recovered when a recovery operation in response to a sudden power off (SPO) is operated (¶[0064] – in response to a power loss indication signal, critical system data or metadata may be saved to non-volatile memory before power is completely lost).
FISHER, CHOI, and KAO are analogous art because they are from the same field of endeavor of management of memory blocks. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of FISHER, CHOI, and KAO before him or her, to modify the metadata associated with block management of the combination of FISHER and CHOI to be saved to non-volatile storage space in response to a power loss as taught by KAO. A motivation for doing so would have been to prevent loss of integrity for already recorded data, data corruption, increased latency, and performance degradation (¶[0016]). Therefore, it would have been obvious to combine FISHER, CHOI, and KAO to obtain the invention as specified in the instant claims.
EXAMINER’S NOTE:
The Office reminds the applicant of MPEP 2111.04(II) regarding the use of contingent limitations in a method (or process) claim:
The broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met. For example, assume a method claim requires step A if a first condition happens and step B if a second condition happens. If the claimed invention may be practiced without either the first or second condition happening, then neither step A or B is required by the broadest reasonable interpretation of the claim. If the claimed invention requires the first condition to occur, then the broadest reasonable interpretation of the claim requires step A. If the claimed invention requires both the first and second conditions to occur, then the broadest reasonable interpretation of the claim requires both steps A and B.
The broadest reasonable interpretation of a system (or apparatus or product) claim having structure that performs a function, which only needs to occur if a condition precedent is met, requires structure for performing the function should the condition occur. The system claim interpretation differs from a method claim interpretation because the claimed structure must be present in the system regardless of whether the condition is met and the function is actually performed.
See Ex parte Schulhauser, Appeal 2013-007847 (PTAB April 28, 2016) for an analysis of contingent claim limitations in the context of both method claims and system claims. In Schulhauser, both method claims and system claims recited the same contingent step. When analyzing the claimed method as a whole, the PTAB determined that giving the claim its broadest reasonable interpretation, "[i]f the condition for performing a contingent step is not satisfied, the performance recited by the step need not be carried out in order for the claimed method to be performed" (quotation omitted). Schulhauser at 10. When analyzing the claimed system as a whole, the PTAB determined that "[t]he broadest reasonable interpretation of a system claim having structure that performs a function, which only needs to occur if a condition precedent is met, still requires structure for performing the function should the condition occur." Schulhauser at 14. Therefore "[t]he Examiner did not need to present evidence of the obviousness of the [ ] method steps of claim 1 that are not required to be performed under a broadest reasonable interpretation of the claim (e.g., instances in which the electrocardiac signal data is not within the threshold electrocardiac criteria such that the condition precedent for the determining step and the remaining steps of claim 1 has not been met);" however to render the claimed system obvious, the prior art must teach the structure that performs the function of the contingent step along with the other recited claim limitations. Schulhauser at 9, 14.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ERIC T LOONAN/Examiner, Art Unit 2137