DETAILED ACTION
This action is responsive to the following: the application filed on August 7, 2024.
Claims 1-20 are pending. Claims 1, 9, and 17 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 5, 7-11, 13, and 15-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lee et al (US 20250227926 A1).
Regarding Independent Claim 1, Lee teaches a memory device (Fig. 1: 100), comprising a first semiconductor structure (Fig. 2: CAS) and a second semiconductor structure (Fig. 2: PCS) coupled with the first semiconductor structure, wherein
the first semiconductor structure (Fig. 2: CAS) comprises a memory array (Fig. 2: 110), word lines (Fig. 2: WL) and bit lines (Fig. 2: BL); wherein the memory array (Fig. 2: 110) comprises memory banks each comprising memory blocks; and the word lines (Fig. 2: WL) and the bit lines (Fig. 2: BL) are coupled to the memory blocks, a length direction of the word lines (Fig. 2: WL) is a first direction, and a length direction of the bit lines (Fig. 2: BL) is a second direction perpendicular to the first direction; and
the second semiconductor structure (Fig. 2: PCS) comprises word line drivers (Fig. 5, 7A: 321, 322) corresponding to each memory block respectively, the word line drivers (Fig. 5, 7A: 321, 322) being coupled with the word lines (Fig. 2: WL); and the word line driver comprises transistors arranged in a third direction perpendicular to the first direction.
Regarding Claim 2, Lee teaches the limitations of Claim 1. Lee further teaches wherein the number of the word line drivers (Fig. 5, 7A: 321, 322) is N and the word line drivers (Fig. 5, 7A: 321, 322) are arranged in the first direction.
Regarding Claim 3, Lee teaches the limitations of Claim 2. Lee further teaches wherein the word line drivers (Fig. 5: 321, 322) are arranged in a row in the first direction.
Regarding Claim 5, Lee teaches the limitations of Claim 1. Lee further teaches wherein the word line drivers (Fig. 5: 321, 322) comprise odd-numbered word line drivers (Fig. 5: 321, 322) and even-numbered word line drivers (Fig. 5: 321, 322), wherein the odd-numbered word line driver is disposed on a side of a corresponding memory block in the first direction, and the even-numbered word line driver is disposed on another side of the corresponding memory block in the first direction (para 142 “As an example of predetermined criteria, in each of the first and second merged sub arrays 501 and 502, the plurality of left word lines WL_L<1>, WL_L<2>, . . . , WL_L<2n−1>, and WL_L<2n> and the plurality of right word lines WL_R<1>, WL_R<2>, . . . , WL_R<2n−1>, and WL_R<2n> may be divided into odd word lines and even word lines”).
Regarding Claim 7, Lee teaches the limitations of Claim 1. Lee further teaches wherein the second semiconductor structure (Fig. 2: PCS) further comprises sense amplifiers (Fig. 10: 311, 312) coupled to the bit lines (Fig. 2: BL); and
the sense amplifiers (Fig. 10: 311, 312) comprise odd-numbered sense amplifiers and even-numbered sense amplifiers (para 112 “ the second bit line half group may divide the plurality of bit lines into odd bit lines and even bit lines. “), wherein the odd-numbered sense amplifier is disposed on a side of a corresponding memory block in the second direction, and the even-numbered sense amplifier is disposed on another side of the corresponding memory block in the second direction.
Regarding Claim 8, Lee teaches the limitations of Claim 1. Lee further teaches wherein the first semiconductor structure (Fig. 2: CAS) and the second semiconductor structure (Fig. 2: PCS) are bonded (para 45 “In some embodiments, the cell array structure CAS and the peripheral circuit structure PCS may adhere to each other through pads in the vertical direction (e.g., the Z direction, first direction). An adhering scheme may be, for example, bonding”).
Regarding Independent Claim 9, Lee teaches a forming method of a memory device (Fig. 1: 100), comprising:
forming a first semiconductor structure (Fig. 2: CAS), wherein the first semiconductor structure (Fig. 2: CAS) comprises a memory array (Fig. 2: 110), word lines (Fig. 2: WL) and bit lines (Fig. 2: BL); wherein the memory array (Fig. 2: 110) comprises memory banks each comprising memory blocks; the word lines (Fig. 2: WL) and the bit lines (Fig. 2: BL) are coupled to the memory blocks, a length direction of the word lines (Fig. 2: WL) is a first direction, a length direction of the bit lines (Fig. 2: BL) is a second direction, and the first direction is perpendicular to the second direction;
forming a second semiconductor structure (Fig. 2: PCS) , wherein the second semiconductor structure (Fig. 2: PCS) comprises word line drivers (Fig. 5: 321, 322) corresponding to each memory block respectively; the word line driver (Fig. 5: 321, 322) comprises transistors arranged in a third direction perpendicular to the first direction; and
bonding (para 45 “In some embodiments, the cell array structure CAS and the peripheral circuit structure PCS may adhere to each other through pads in the vertical direction (e.g., the Z direction, first direction). An adhering scheme may be, for example, bonding”) the first semiconductor structure (Fig. 2: CAS) and the second semiconductor structure (Fig. 2: PCS) .
Regarding Claim 10, Lee teaches the limitations of Claim 9. Lee further teaches wherein the first semiconductor structure (Fig. 2: CAS) and the second semiconductor structure (Fig. 2: PCS) are bonded (para 45 “In some embodiments, the cell array structure CAS and the peripheral circuit structure PCS may adhere to each other through pads in the vertical direction (e.g., the Z direction, first direction). An adhering scheme may be, for example, bonding”).
Regarding Claim 11, Lee teaches the limitations of Claim 10. Lee further teaches wherein the word line drivers (Fig. 5: 321, 322) are arranged in a row of in the first direction.
Regarding Claim 13, Lee teaches the limitations of Claim 9. Lee further teaches wherein the word line drivers (Fig. 5: 321, 322) comprise odd-numbered word line drivers (Fig. 5: 321, 322) and even-numbered word line drivers (Fig. 5: 321, 322), wherein the odd-numbered word line driver is disposed on a side of a corresponding memory block in the first direction, and the even-numbered word line driver is disposed on another side of the corresponding memory block in the first direction (para 142 “As an example of predetermined criteria, in each of the first and second merged sub arrays 501 and 502, the plurality of left word lines WL_L<1>, WL_L<2>, . . . , WL_L<2n−1>, and WL_L<2n> and the plurality of right word lines WL_R<1>, WL_R<2>, . . . , WL_R<2n−1>, and WL_R<2n> may be divided into odd word lines and even word lines”).
Regarding Claim 15, Lee teaches the limitations of Claim 9. Lee further teaches wherein the second semiconductor structure (Fig. 2: PCS) further comprises sense amplifiers (Fig. 10: 311, 312) coupled to the bit lines (Fig. 2: BL); and
the sense amplifiers comprise (Fig. 10: 311, 312) odd-numbered sense amplifiers and even-numbered sense amplifiers (para 112 “ the second bit line half group may divide the plurality of bit lines into odd bit lines and even bit lines. “), wherein the odd-numbered sense amplifier is disposed on a side of a corresponding memory block in the second direction, and the even-numbered sense amplifier is disposed on another side of the corresponding memory block in the second direction.
Regarding Claim 16, Lee teaches the limitations of Claim 9. Lee further teaches wherein the first semiconductor structure (Fig. 2: CAS) is formed on a first wafer, and the second semiconductor structure (Fig. 2: PCS) is formed on a second wafer; and
bonding the first semiconductor structure (Fig. 2: CAS) and the second semiconductor structure (Fig. 2: PCS) further comprises:
bonding (para 45 “In some embodiments, the cell array structure CAS and the peripheral circuit structure PCS may adhere to each other through pads in the vertical direction (e.g., the Z direction, first direction). An adhering scheme may be, for example, bonding”) the first wafer (Fig. 2: CAS) and the second wafer (Fig. 2: PCS) and cutting the first wafer and the second wafer.
Regarding Independent Claim 17, Lee teaches a memory system, comprising:
a memory controller (Fig. 11: 2810); and
a memory device (Fig. 1: 100) coupled with the memory controller, the memory device comprising:
a first semiconductor structure (Fig. 2: CAS) and a second semiconductor structure (Fig. 2: PCS) , the first semiconductor structure (Fig. 2: CAS) being coupled with the second semiconductor structure (Fig. 2: PCS) , wherein:
the first semiconductor structure (Fig. 2: CAS) comprises a memory array (Fig. 2: 110), word lines (Fig. 2: WL) and bit lines (Fig. 2: BL); wherein the memory array (Fig. 2: 110) comprises memory banks each comprising memory blocks; and the word lines (Fig. 2: WL) and the bit lines (Fig. 2: BL) are coupled to the memory blocks, a length direction of the word lines (Fig. 2: WL) is a first direction, and a length direction of the bit lines (Fig. 2: BL) is a second direction perpendicular to the first direction; and
the second semiconductor structure (Fig. 2: PCS) comprises word line drivers (Fig. 5: 321, 322) corresponding to each memory block respectively, the word line drivers (Fig. 5: 321, 322) being coupled with the word lines (Fig. 2: WL); and the word line driver comprises transistors arranged in a third direction perpendicular to the first direction; and
wherein the memory controller is configured to control the memory.
Regarding Claim 18, Lee teaches the limitations of Claim 17. Lee further teaches wherein the number of the word line drivers (Fig. 5: 321, 322) is N and the word line drivers (Fig. 5: 321, 322) are arranged in the first direction.
Regarding Claim 19, Lee teaches the limitations of Claim 17. Lee further teaches wherein the word line drivers (Fig. 5: 321, 322) comprise odd-numbered word line drivers (Fig. 5: 321, 322) and even-numbered word line drivers (Fig. 5: 321, 322), wherein the odd-numbered word line driver is disposed on a side of a corresponding memory block in the first direction, and the even-numbered word line driver is disposed on another side of the corresponding memory block in the first direction (para 142 “As an example of predetermined criteria, in each of the first and second merged sub arrays 501 and 502, the plurality of left word lines WL_L<1>, WL_L<2>, . . . , WL_L<2n−1>, and WL_L<2n> and the plurality of right word lines WL_R<1>, WL_R<2>, . . . , WL_R<2n−1>, and WL_R<2n> may be divided into odd word lines and even word lines”).
Regarding Claim 20, Lee teaches the limitations of Claim 17. Lee further teaches wherein the first semiconductor structure (Fig. 2: CAS) and the second semiconductor structure (Fig. 2: PCS) are bonded (para 45 “In some embodiments, the cell array structure CAS and the peripheral circuit structure PCS may adhere to each other through pads in the vertical direction (e.g., the Z direction, first direction). An adhering scheme may be, for example, bonding”).
Allowable Subject Matter
Claims 4, 6, 12 and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 4 and 12 would be allowable for teaching that there are two rows of word lines drivers, where the rows are arranged in the first direction parallel to the word lines. And the that there are two rows of word line drivers are arranged relative to each other in the second direction. Lee does not teach that the word line drivers are in two rows that run parallel to the word lines. Therefore, these claims would be allowable if written in independent form.
Claims 6 and 14 would be allowable for teaching that the sum of the length of the row decoder and length of the word line drivers is less than the length of the memory block in the direction that runs parallel to the bit lines. Lee is silent with respect to the lengths of word line driver blocks and decoder blocks relative to the memory block as a whole. Therefore, these claims would be allowable if written in independent form.
Conclusion
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/JOSEPH FIDELIS STORMES/Examiner, Art Unit 2825
/Donald HB Braswell/Primary Examiner, Art Unit 2825
Prosecution Insights