DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 3-5, 7, 10, and 12-15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 3-4, 10, and 12-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shen et al. (US 2018/0167073), in view of Alpman et al. (WO 2018/119153).
In regard to Claim 1:
Shen discloses, in Figure 1, a control arrangement for providing a plurality of phase-coherent oscillating signals, the control arrangement comprising: a reference clock input arrangement (162) for providing a high-frequency reference clock signal (121), a plurality of modules (126-1, 126-2, 126-3) each comprising a plurality of channels (126-1, 126-2, 126-3 channels) for providing the plurality of phase-coherent oscillating signals (127-1, 127-2, 127-3), a first distribution arrangement (124) for distributing the high-frequency reference clock signal (121 via 122) in a phase-coherent manner to the plurality of modules (126-1, 126-2, 126-3), a second distribution arrangement (Figure 4A: 408; Figure 4A is the detailed view of 126(1-3)) for distributing the high-frequency reference clock signal (123 via 124) in a phase-coherent manner to the plurality of channels of the respective module (127-1, 127-2, 127-3), and a first phase-locked loop (122) configured to upconvert the high-frequency reference clock signal (121) for providing one of the plurality of phase-coherent oscillating signals (127-1, 127-2, 127-3), but does not disclose a high-frequency reference clock signal at an accuracy of 20 ppm (+/-) or better.
Alpman discloses a high-frequency reference clock signal at an accuracy of 20 ppm (+/-) or better (¶ 01946: lines 14-17).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the reference clock with 20 ppm (+/-) or better taught by Alpman with the reference clock input arrangement taught by Shen, since all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination yielded nothing more than predictable results to one of ordinary skill in the art. (KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385).
In regard to Claim 3:
All of the claim limitations have been discussed with respect to Claim 1 above, except for wherein reference clock input arrangement comprises a motherboard arrangement and wherein each of the plurality of modules comprises a circuit board.
Shen further discloses, in Figure 1, the control arrangement according to claim 1, wherein reference clock input arrangement comprises a motherboard arrangement and wherein each of the plurality of modules comprises a circuit board (Paragraph 0003, where the sub-PLL circuits are included on a system on chip (SOC) to connected to CPU, GPU, SATA which are found on a motherboard).
In regard to Claim 4:
All of the claim limitations have been discussed with respect to Claim 1 above, except for wherein reference clock input arrangement comprises a motherboard arrangement and wherein the plurality of modules is arranged for pluggable coupling to the motherboard arrangement.
Shen further discloses, in Figure 1, the control arrangement according to claim 1, wherein reference clock input arrangement comprises a motherboard arrangement and wherein the plurality of modules is arranged for pluggable coupling to the motherboard arrangement (Paragraph 0003, where the sub-PLL circuits are included on a system on chip (SOC) to connected to CPU, GPU, SATA which are pluggable on a motherboard).
In regard to Claim 10:
All of the claim limitations have been discussed with respect to Claim 1 above, except for a generator arrangement for providing a plurality of phase-coherent oscillating signals, the generator arrangement comprising the control arrangement according to claim 1 and a reference clock generator arranged for providing a reference clock signal for providing the high-frequency reference clock signal.
Shen further discloses, in Figure 1, a generator arrangement for providing a plurality of phase-coherent oscillating signals (127-1, 127-2, 127-3), the generator arrangement comprising the control arrangement according to claim 1 (see the rejection of Claim 1 above) and a reference clock generator (164) arranged for providing a reference clock signal (164 output) for providing the high-frequency reference clock signal (162 produces high-frequency reference clock 121).
In regard to Claim 12:
Shen discloses, in Figure 1, a method for providing a plurality of phase-coherent oscillating signals (127-1, 127-2, 127-3), the method comprising: receiving a high-frequency reference clock signal (121), distributing (124) the high-frequency reference clock signal (121) in a phase-coherent manner to a plurality of modules (126-1, 126-2, 126-3), distributing (Figure 4A: 408; Figure 4A is the detailed view of 126(1-3)) the high-frequency reference clock signal (121) in a phase-coherent manner to a plurality of channels of the respective module (126-1, 126-2, 126-3 channels), and upconverting (122) the high-frequency reference clock signal (121) for providing one of the plurality of phase-coherent oscillating signals (127-1, 127-2, 127-3), but does not disclose a high-frequency reference clock signal at an accuracy of 20 ppm (+/-) or better.
Alpman discloses a high-frequency reference clock signal at an accuracy of 20 ppm (+/-) or better (¶ 01946: lines 14-17).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the reference clock with 20 ppm (+/-) or better taught by Alpman with the reference clock input arrangement taught by Shen, since all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination yielded nothing more than predictable results to one of ordinary skill in the art. (KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385).
In regard to Claim 13:
All of the claim limitations have been discussed with respect to Claim 1 above, except for receiving an initial reference clock signal, and upconverting the initial reference clock signal for providing the high-frequency reference clock signal.
Shen further discloses, in Figure 1, the method according to claim 12, comprising: receiving an initial reference clock signal (164 output), and upconverting (162) the initial reference clock signal (164 output) for providing the high-frequency reference clock signal (121).
Claim(s) 7, 14, and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shen et al. (US 2018/0167073) and Alpman et al. (WO 2018/119153).
In regard to Claim 7:
All of the claim limitations have been discussed with respect to Claim 1 above, except for wherein the high-frequency reference clock signal has a frequency of 100-250 MHz and/or the plurality of phase-coherent oscillating signals has a frequency of 1-15 GHz. It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to have the high-frequency reference clock signal have a frequency of 100-250 MHz and/or the plurality of phase-coherent oscillating signals have a frequency of 1-15 GHz, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. Further it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to have the high-frequency reference clock signal have a frequency of 100-250 MHz and/or the plurality of phase-coherent oscillating signals have a frequency of 1-15 GHz, in order to advantageously eliminate the jitter noise (Shen Paragraph 0046).
In regard to Claim 14:
All of the claim limitations have been discussed with respect to Claim 13 above, except for wherein the initial reference clock signal has a frequency of 5-50 MHz. It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to the initial reference clock signal have a frequency of 5-50 MHz, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. Further it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to have the high-frequency reference clock signal have a frequency of 100-250 MHz and/or the plurality of phase-coherent oscillating signals have a frequency of 1-15 GHz, in order to advantageously eliminate the jitter noise (Shen Paragraph 0046).
In regard to Claim 15:
All of the claim limitations have been discussed with respect to Claim 12 above, except for wherein the high-frequency reference clock signal has a frequency of 100-250 MHz and/or the plurality of phase-coherent oscillating signals has a frequency of 1-15 GHz. It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to have the high-frequency reference clock signal have a frequency of 100-250 MHz and/or the plurality of phase-coherent oscillating signals have a frequency of 1-15 GHz, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. Further it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to have the high-frequency reference clock signal have a frequency of 100-250 MHz and/or the plurality of phase-coherent oscillating signals have a frequency of 1-15 GHz, in order to advantageously eliminate the jitter noise (Shen Paragraph 0046).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shen et al. (US 2018/0167073) and Alpman et al. (WO 2018/119153), in view of Peckman (US 2019/0162841).
In regard to Claim 5:
All of the claim limitations have been discussed with respect to Claim 1 above, except for wherein each of the plurality of modules comprises a plurality of shields for radio-frequency (rf) shielding of each of the plurality of channels of the respective module.
Peckman discloses wherein each of the plurality of modules comprises a plurality of shields for radio-frequency (rf) shielding (Paragraph 0111, where the transponder of Figure 3A is mounted on circuit board 602) of each of the plurality of channels of the respective module (Paragraph 0076 and Figure 3A: 334).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the RF shield and housing taught by Peckman with the clock distribution circuit taught by Shen and Alpman, to provide improved performance in radio-frequency-dense environments (e.g., improved cohabitation characteristics) and improved operation in high-powered radio-frequency environments (e.g., improved survivability characteristics) (Peckman Paragraph 0032).
Allowable Subject Matter
Claims 2, 6, 8-9, 11, and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to John W Poos whose telephone number is (571)270-5077. The examiner can normally be reached M-Th 8-5.
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/JOHN W POOS/Primary Examiner, Art Unit 2896
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