DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to applicant’s communication filed 9/29/2025 in response to PTO Office Action mailed 6/30/2025. The applicant’s remarks and amendments to the claims and/or specification were considered with the results that follow.
In response to last Office Action, claims 1, 9 and 14 have been amended. Claim 12 has been canceled. No claims have been added. As a result, claims 1-11 and 13-20 remain pending in this application.
Response to Arguments
Applicant’s arguments with respect to claims 1, 9 and 14 have been considered but they are moot in view of the new ground(s) of rejection(s).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 4, 14, 15 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2014/0149827) and further in view of Kim et al. (US 2019/0163650) (Kim ‘650 herein after).
As per claim 1, Kim teaches a processor (Kim: fig. 2B; item 150), comprising: a first cache (Kim: fig. 2B; item 111) including a first cell array and a first peripheral circuit, the first peripheral circuit being electrically connected to the first cell array; and a second cache (Kim: fig. 2B; item 112) including a second cell array and a second peripheral circuit, the second peripheral circuit being electrically connected to the second cell array and different from the first peripheral circuit, each of the first cell array and the second cell array including magnetic random-access memory (MRAM) cells (Kim: par. [0083]: “each of the first and second caches 111 and 112 may include the MRAM device and the controller. Alternatively, while the MRAM device including the MRAM cell array may be embodied in both of the first and second caches 111 and 112”; par. [0084]: “FIG. 3 is a block diagram schematically illustrating an example of an MRAM device included in any one of the cache memories of FIGS. 1-2B”; par. [0086]: “the MRAM device 300 includes a command decoder 310, an address buffer 320, a row decoder 330, a column decoder 340, a cell array 350”).
Kim fails teach wherein the first peripheral circuit and the second peripheral circuit differ according to operational characteristics including (i) speed of reading and writing data and (ii) retention period.
Kim ‘650 teaches wherein the first peripheral circuit and the second peripheral circuit differ according to operational characteristics including (i) speed of reading and writing data (Kim: pars. [0038], [0054], [0056]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide the first and second peripheral circuits according to operational speed of the memories as taught by Kim ‘650 to improve the performance of the memory system because the speed of the memory and the speed of the peripheral circuits are interdependent. If peripheral circuits were slower than the memory itself, they would become the limiting factor in overall performance.
Kim and Kim ‘650 expressly fails to teach wherein the first peripheral circuit and the second peripheral circuit differ according to operational characteristics including (ii) retention period. However, as explained above, the characteristics of the peripheral circuits must match because the peripheral circuits must operate to reliably read and write the data stored in the memory cells and the memory cells’ retention level determines how long data can be reliably stored. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide the first and second peripheral circuits according to provide the peripheral circuits to match the retention levels of respective memory cells to improve the overall reliability of the memory system.
As per claim 2, Kim teaches wherein the first cache and the second cache have different read speeds (Kim: par. [0083]: “a first cache (L1 cache) 111 that is relatively fast and a second cache (L2 cache) 112 that is relatively slow but has a relatively large capacity”).
As per claim 4, Kim teaches wherein the first and second caches are on a same semiconductor chip (par. [0083]: “FIG. 2B illustrates an example in which the cache memory 110 is included in the CPU 150. Also, in the example, the cache memory 110 includes at least two caches in the CPU 150”).
As per claim 14, Kim teaches An electronic device (Kim: fig. 1, par. [0049]), comprising: a processor (Kim: fig. 2B, item 150) including at least one core (Kim: fig. 2B, item 151) and first and second caches (Kim: fig. 2B, items 111, 112), each of the first cache and the second cache including magnetic random-access memory (MRAM) cells and a peripheral circuit (please refer to claim 1 above); and a main memory configured to communicate with the processor (Kim: fig. 2B, item 140).
As per claim 15, Kim teaches wherein the processor is on a single semiconductor chip (par. [0083]: “FIG. 2B illustrates an example in which the cache memory 110 is included in the CPU 150. Also, in the example, the cache memory 110 includes at least two caches in the CPU 150”).
As per claim 18, Kim teaches wherein the first cache and the second cache have different read speeds (Kim: par. [0083]: “a first cache (L1 cache) 111 that is relatively fast and a second cache (L2 cache) 112 that is relatively slow but has a relatively large capacity”).
Claims 3, 5, 6, 8, 9-11, 13, 17, 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2014/0149827) and Kim et al. (US 2019/0163650) (Kim ‘650 herein after) as applied to claims 1, 2 and 14 above, and further in view of Kang et al. (US 9,196,334) (IDS reference).
As per claim 3, Kim teaches wherein the read speed of the first cache is slower than the read speed of the second cache (Kim: par. [0083]: “a first cache (L1 cache) 111 that is relatively fast and a second cache (L2 cache) 112 that is relatively slow but has a relatively large capacity”). However, Kim fails to teach a retention period of the first cache is longer than a retention period of the second cache.
Kang teaches wherein a retention period of the first cache is longer than a retention period of the second cache (Kang: col. 2, lines 25-44). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide first and second cache memories with different retention periods as taught by Kang to provide the storage performance based on the level of the memory hierarchy (Kang: col. 1, line 65 – col. 2, line 10).
As per claim 5, Kim fails to teach the processor of claim 1, further comprising: a third cache including a third cell array and a third peripheral circuit, the third peripheral circuit being electrically connected to the third cell array and including MRAM cells.
Kang teaches the processor of claim 1, further comprising: a third cache including a third cell array and a third peripheral circuit, the third peripheral circuit being electrically connected to the third cell array and including MRAM cells (Kang: col. 5, lines 16-35: L1, L2 and L3 caches). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide a third cache as taught by Kang to improve system performance by providing multiple levels of caches with differing levels of performance and capacities.
As per claim 6, Kim and Kang teach wherein the first cache, the second cache, and the third cache have different read speeds (Kang: col. 5, lines 35-47; .
Claims 17 and 20 are similar in scope with claims 5 and 6 above and thus rejected under same rationales as applied to claims 5 and 6 above.
As per claim 9, Kim and Kang teach a processor, comprising: at least one core; and a cache memory including L1, L2, and L3 caches and a first cache, each of the L3 cache and the first cache including magnetic random-access memory (MRAM) cells (As explained with respect to claim 5 above, Kim and Kang teach a processor comprising at least one core and L1, L2 and L3 caches with MRAM cells and Kang further teaches M or N levels of caches (Kang: fig. 5), where it would be readily apparent to one having ordinary skill in the art to have another level of cache (e.g., first cache) by increasing storage capacity and the performance of the system.
Kim and Kang expressly fail to teach the at least one core is configured to access the L3 cache before accessing the first cache. However, it is well-known in the art of caches to access upper level caches first e.g., accessing L3 cache first, before accessing the lower level (first) cache, as the L3 cache is near the processor compared to first cache and it is faster compared to the first cache.
Claims 10-11 and 3 are similar in scope with claims 2-6 above and thus rejected under same rationales as applied to claims 2-6 above.
As per claim 8, Kim and Kang expressly fail to teach wherein the first cache or the second cache is configured to store programs for booting. However, storing type of data in a memory is an intended use. Since, MRAM is type of non-volatile memory and can be accessed at higher speed, therefore one having ordinary skill in the art would be motivated to use the first or second cache to store programs for booting.
Claim 19 is rejected under same rationales as applied to claim 8 above.
Claims 7 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2014/0149827) and Kim et al. (US 2019/0163650) (Kim ‘650 herein after) as applied to claims 1 and 14 above, and further in view of Nakahara et al. (US 2023/0143732) (IDS reference).
As per claim 7, Kim fails to teach the processor of claim 1, further comprising: a third cache including a third cell array and a third peripheral circuit, the peripheral circuit being electrically connected to the third cell array and including static random-access memory (SRAM) cells.
Nakahara teaches multiple caches (fig. 1, items 112, 124 and 126) with different types of memory cell arrays and combination of cell arrays (SRAM and MRAM) (Nakahara: par. [0055]). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention would be motivated to provide combination of cache memories with different types of memory cell arrays as taught by Nakahara to improve the access efficiency while reducing the increase in circuit size (Nakahara: par. [0023]).
Claim 16 is rejected under same rationales as applied to claim 7 above.
Conclusion
The examiner also requests, in response to this Office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line no(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application. 37 C.F.R. § 1.75(d) (1) requires such support in the Specification for any new language added to the claims and 37 C.F.R. § 1.83(a) requires support be found in the Drawings for all claimed features.
When responding to this office action, Applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of the art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections See 37 CFR 1.111(c).
Examiner has cited particular columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant, in preparing the responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KAUSHIKKUMAR M PATEL whose telephone number is (571)272-5536. The examiner can normally be reached Mon-Fri: 9:00 AM - 5:30 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tim T Vo can be reached at 571-272-3642. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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Kaushikkumar M. Patel
Primary Examiner
Art Unit 2138
/Kaushikkumar M Patel/Primary Examiner, Art Unit 2138