Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Election/Restrictions
Newly submitted claims 24-26 directed to a non-elected species originally claimed for the following reasons:
Original claim 10, filed November 20, 2025, which was rolled up into claim 1, filed March 17, 2026, has been amended and rolled down to new claim 22, filed July 23, 2026. Original claim 13 (withdrawn), filed November 20, 2025, which depended on original claim 10, was amended to depend on claim 1, filed March 17, 2026; has been cancelled and rolled down to new claim 24. Since the original claim 13, which depended on the original claim 10, was withdrawn as being drawn to a non-elected species, therefore the new claim 24, and it’s dependent claims 25-26, shall be withdrawn from consideration.
Since applicant has received an action on the merits for the originally presented invention, this invention has been constructively elected by original presentation for prosecution on the merits. Accordingly, claims 24-26 are withdrawn from consideration as being directed to a non-elected invention. See 37 CFR 1.142(b) and MPEP § 821.03.
Response to Arguments
Applicant’s arguments, see Drawings (page 15 of 26), filed July 23, 2026, with respect to duplicate designations in multiple buffer branches of multiple figures have been fully considered and are persuasive. The objection of May 1, 2026 has been withdrawn.
Applicant’s arguments with respect to amended claim 1 have been considered but are moot because of the new ground of rejection.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the width of a channel of the first transistor is greater than a width of a channel of the second transistor must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required: a width of a channel of the first transistor is greater than a width of a channel of the second transistor.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 1 (lines 26-27) rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
The claim recites "a width of a channel of the first transistor is greater than a width of a channel of the second transistor". There is a lack of written description as to "a width of a channel of the first transistor is greater than a width of a channel of the second transistor". Although, the width of a channel of a transistor is disclosed in paragraph [0089], the paragraph refers to non-elected species Fig. 15, as well as the sixth transistor T6 and seventh transistor T7; and not to the elected species Fig. 13, with the first transistor T1 and the second transistor T2. The elected species Fig. 13 is described in paragraph [0097] where the width-to-length ratio of a fifth transistor T5 in the (i+1)-th buffer branch 30 is greater than the width-to-length ratio of a fifth transistor T5 in the i-th buffer branch 30; but again, these are not what is claimed where the first transistor T1 is in the first voltage division branch 10 and the second transistor T2 is in the second voltage division branch 20; and this is describing width-to-length ratio and not width of a channel. Thus, the specification fails to provide a demonstration of possession.
Claims 2-9 and 16-26 inherit the defects of the rejected claim 1 and/or any intervening claims.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as failing to set forth the subject matter which the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the applicant regards as the invention.
Claim 1 (lines 26-27) recites "a width of a channel of the first transistor is greater than a width of a channel of the second transistor". It's unclear from the description and drawings where this is shown in the elected species.
Claims 2-9 and 16-26 inherit the defects of the rejected claim 1 and/or any intervening claims.
Claim Rejections - 35 USC § 103
Applicant is reminded that claim mapping is provided as a courtesy to the applicant, but applicant should consider a reference as a whole, as the entire reference gives context to mapped sections.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 5, 7, and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Thakur et al. (US 9337818 B1), hereinafter Thakur; in view of Shenai et al. (US 6608503 B2), hereinafter Shenai; further in view of Bui (US 6147513 A), hereinafter Bui.
Regarding Claim 1, as best understood, Thakur discloses a circuit structure [Fig. 4, 410], comprising a first voltage division branch [418] and a second voltage division branch [420];
wherein a first terminal [supply voltage terminal of 418] of the first voltage division branch receives a first power signal [signal into VDD_2 terminal], a voltage of the first power signal is V1 [VDD_2], a second terminal [ground terminal of 418] of the first voltage division branch receives a second power signal [signal into ground terminal of 418], a voltage of the second power signal is V2 [ground], a first terminal [voltage terminal of 420] of the second voltage division branch receives a third power signal [signal into V_DL terminal], a voltage of the third power signal is V3 [V_DL], and a second terminal [ground terminal below of 420] of the second voltage division branch receives a fourth power signal [signal into ground terminal of 420], and a voltage of the fourth power signal is V4 [ground], wherein V1> V2, and V3>V4;
the first voltage division branch comprises a first control terminal [input terminal of 418] and a first voltage division output terminal [output terminal of 418], and the second voltage division branch comprises a second control terminal [input terminal of 420] and a second voltage division output terminal [output terminal of 420], wherein the first control terminal receives a first initial signal [column 8, lines 21-22; input clock signal] at a voltage being V0 [Vinput_clk], and the first voltage division output terminal is electrically connected to the second control terminal [column 8, lines 21-28];
the first initial signal comprises a first pulse level stage and a second pulse level stage [column 8, lines 21-28]; and
the first voltage division branch and the second voltage division branch are configured to perform the following operations:
at the first pulse level stage, outputting a first output level signal by the second voltage division output terminal under control of an output signal of the first voltage division output terminal; and at the second pulse level stage, outputting a second output level signal by the second voltage division output terminal under the control of the output signal of the first voltage division output terminal, wherein the first output level signal and the second output level signal are different [one of ordinary skill in the art understands the inverter functionality converts high/low and low/high].
As shown in the rejection above, Thakur discloses an inverter for both the first voltage division branch and the second voltage division branch. As one of ordinary skill in the art understands, the internal components of the inverter can vary.
Thakur does not explicitly disclose a first transistor within the first voltage division branch, a second transistor within the second voltage division branch, and a width of a channel of the first transistor is greater than a width of a channel of the second transistor.
However, Shenai discloses many configurations of internal components of an inverter [specifically, the inverters in Fig. 5E & 5J]. For the first voltage division branch [Thakur; 418], Shenai discloses a first transistor [Fig. 5E, NMOS transistor]. For the second voltage division branch [Thakur; 420] Shenai discloses a second transistor [Fig. 5J, PMOS transistor].
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to use the invention of Shenai in the invention of Thakur, with the expected benefit of circuit simplicity. This method of improving Thakur using Shenai was within the ordinary ability of one of ordinary skill in the art before the effective filing date of the claimed invention based on the teachings of Shenai. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Thakur and Shenai to obtain the invention: incorporating the inverters of Shenai as identified above.
Thakur, in view of Shenai, discloses the claimed invention except for a width of a channel of the first transistor is greater than a width of a channel of the second transistor. It would have been obvious to one having ordinary skill in the art at the time the invention was made to compare a width of a channel of the first transistor with a width of a channel of the second transistor, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. Bui discloses that varying the betas of transistors, the designer can alter characteristics of the circuit [column 1, lines 46-57; column 1, line 60 - column 2, line 3; column 3, lines 16-22].
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to use the invention of Bui in the invention of Thakur, in view of Shenai, with the expected benefit of having the most favorable characteristic outcomes. This method of improving Thakur, in view of Shenai, using Bui was within the ordinary ability of one of ordinary skill in the art before the effective filing date of the claimed invention based on the teachings of Bui. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Thakur, in view of Shenai, and Bui to obtain the invention: incorporating varying widths of channels of NMOS and PMOS transistors [Bui; column 4, lines 8-13].
Regarding Claim 2, as best understood, the combined art of Thakur, Shenai and Bui in claim 1 discloses the circuit structure according to claim 1, wherein
the first voltage division branch comprises a first voltage division unit [Shenai; Fig. 5E, resistor] and a second voltage division unit [Shenai; Fig. 5E, NMOS transistor], wherein a connection node between the first voltage division unit and the second voltage division unit is the first voltage division output terminal [Shenai; Fig. 5E, node Y] / [Thakur; Fig. 4, output terminal of 418], at least one of the first voltage division unit or the second voltage division unit comprises the first control terminal [Shenai; Fig. 5E, input of T into gate of NMOS transistor]; and
the second voltage division branch comprises a third voltage division unit [Shenai; Fig. 5J, PMOS transistor] and a fourth voltage division unit [Shenai; Fig. 5J, resistor], wherein a connection node between the third voltage division unit and the fourth voltage division unit is the second voltage division output terminal [Shenai; Fig. 5J, node Y] / [Thakur; Fig. 4, output terminal of 420], at least one of the third voltage division unit or the fourth voltage division unit comprises the second control terminal [Shenai; Fig. 5J, input T into gate of PMOS transistor].
Regarding Claim 3, as best understood, understood, the combined art of Thakur, Shenai and Bui in claim 1 discloses the circuit structure according to claim 2, wherein the first voltage division unit comprises a first resistor [Shenai, Fig. 5E, resistor] , and the second voltage division unit comprises the first transistor, wherein the first voltage division branch satisfies at least one of: a resistance of the first resistor ranges from 106 Ω to 108 Ω, or, the first transistor is an N-type channel transistor [Shenai; Fig. 5E, column 3, lines 53-55];
wherein a first terminal of the first resistor [Shenai; Fig. 5E, top terminal of resistor] receives the first power signal, a second terminal of the first resistor [Shenai; Fig. 5E, bottom terminal of resistor] is electrically connected to a first electrode of the first transistor [Shenai; Fig. 5E, drain of NMOS transistor], and a second electrode of the first transistor [Shenai; Fig. 5E, source of NMOS transistor] receives the second power signal; and
wherein a gate of the first transistor [Shenai; Fig. 5E, gate of NMOS transistor] is served as the first control terminal, and the gate of the first transistor receives the first initial signal.
Regarding Claim 5, as best understood, the combined art of Thakur, Shenai and Bui in claim 1 discloses the circuit structure according to claim 2, wherein the third voltage division unit comprises the second transistor, and the fourth voltage division unit comprises a second resistor [Shenai; Fig. 5J, resistor], wherein the second voltage division branch satisfies at least one of: a resistance of the second resistor ranges from 106 Ω to 108 Ω, or the second transistor is a P-type channel transistor [Shenai; Fig. 5J, column 3, lines 55-57];
wherein a first electrode of the second transistor [Shenai; Fig. 5J, source of PMOS transistor] receives the third power signal, a second electrode of the second transistor [Shenai; Fig. 5J, drain of PMOS transistor] is electrically connected to a first terminal of the second resistor [Shenai; Fig. 5J, top terminal of resistor], and a second terminal of the second resistor [Shenai; Fig. 5J, bottom terminal of resistor] receives the fourth power signal; and
wherein a gate of the second transistor [Shenai; Fig. 5J, gate of PMOS transistor], as the second control terminal, is electrically connected to the first voltage division output terminal.
Regarding Claim 7, as best understood, the combined art of Thakur, Shenai and Bui in claim 1 discloses the circuit structure according to claim 1, wherein V2≤V4 [Shenai, Fig. 5E/5J, V2=V4=a ground voltage]. The combined art of Thakur, Shenai and Bui in claim 1 does not explicitly disclose wherein V1≥V3. It would have been obvious to one having ordinary skill in the art at the time the invention was made to have the two voltages either equal to each other, or greater than each other, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding Claim 16, as best understood, the combined art of Thakur, Shenai and Bui in claim 1 discloses a device [Thakur; Fig. 4, 402], comprising the circuit structure according to claim 1 [see Claim 1 rejection above].
Claim(s) 8-9 and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combined art of Thakur, Shenai and Bui in claim 1, in view of Xi et al. (US 20200316590 A1), hereinafter Xi.
Regarding Claim 8, as best understood, the combined art of Thakur, Shenai and Bui in claim 1 does not explicitly disclose the circuit structure according to claim 2, wherein the circuit structure further comprises a base substrate, wherein the first voltage division branch and the second voltage division branch are located on a same side of the base substrate;
an orthographic projection of the first voltage division unit on a plane where the base substrate is located is adjacent to an orthographic projection of the second voltage division unit on the plane where the base substrate is located in a first direction, and an orthographic projection of the third voltage division unit on the plane where the base substrate is located is adjacent to an orthographic projection of the fourth voltage division unit on the plane where the base substrate is located in the first direction;
an orthographic projection of a composite structure of the first voltage division unit and the second voltage division unit on the plane where the base substrate is located is adjacent to an orthographic projection of a composite structure of the third voltage division unit and the fourth voltage division unit on the plane where the base substrate is located in a second direction; and
the first direction and the second direction intersect with each other and are both parallel to the plane where the base substrate is located.
However, Xi discloses wherein the circuit structure further comprises a base substrate, wherein the first voltage division branch and the second voltage division branch are located on a same side of the base substrate [paragraph 0009, 0087];
an orthographic projection of the first voltage division unit on a plane where the base substrate is located is adjacent to an orthographic projection of the second voltage division unit on the plane where the base substrate is located in a first direction, and an orthographic projection of the third voltage division unit on the plane where the base substrate is located is adjacent to an orthographic projection of the fourth voltage division unit on the plane where the base substrate is located in the first direction [paragraphs 0120-0121];
an orthographic projection of a composite structure of the first voltage division unit and the second voltage division unit on the plane where the base substrate is located is adjacent to an orthographic projection of a composite structure of the third voltage division unit and the fourth voltage division unit on the plane where the base substrate is located in a second direction; and
the first direction and the second direction intersect with each other and are both parallel to the plane where the base substrate is located [paragraphs 0120-0121].
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to use the invention of Xi in the invention of the combined art of Thakur, Shenai and Bui in claim 1, with the expected benefit of design optimization. This method of improving the combined art of Thakur, Shenai and Bui in claim 1 using Xi was within the ordinary ability of one of ordinary skill in the art before the effective filing date of the claimed invention based on the teachings of Xi. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of the combined art of Thakur, Shenai and Bui in claim 1 and Xi to obtain the invention: incorporating a base substrate with its components.
Regarding Claim 9, as best understood, the combined art of Thakur, Shenai and Bui in claim 1, in view of Xi, discloses the circuit structure according to claim 8, wherein at least one of the first voltage division unit or the fourth voltage division unit comprises a resistor [Shenai; Fig. 5E, resistor (first voltage division unit); Fig. 5J, resistor (fourth voltage division unit)], wherein an orthographic projection of the resistor on the plane where the base substrate is located extends in a zigzag manner [Xi; paragraph 0120-0121 states the shape orthographically projected on the substrate may be a semicircle or crescent].
Regarding Claim 21, as best understood, the combined art of Thakur, Shenai and Bui in claim 1 does not explicitly disclose the circuit structure according to claim 2, wherein the circuit structure further comprises a base substrate, wherein the first voltage division branch and the second voltage division branch are located on a same side of the base substrate; and
in a direction perpendicular to a plane where the base substrate is located, a film where the second voltage division branch is located is located between the base substrate and the film where the first voltage division branch is located, and an orthographic projection of the first voltage division branch on the plane where the base substrate is located at least partially overlaps an orthographic projection of the second voltage division branch on the plane where the base substrate is located.
However, Xi discloses wherein the circuit structure further comprises a base substrate, wherein the first voltage division branch and the second voltage division branch are located on a same side of the base substrate; and in a direction perpendicular to a plane where the base substrate is located, a film where the second voltage division branch is located is located between the base substrate and the film where the first voltage division branch is located, and an orthographic projection of the first voltage division branch on the plane where the base substrate is located at least partially overlaps an orthographic projection of the second voltage division branch on the plane where the base substrate is located [paragraphs 0009, 0087-0089, 0102, 0120-0121].
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to use the invention of Xi in the invention of the combined art of Thakur, Shenai and Bui in claim 1, with the expected benefit of design optimization. This method of improving the combined art of Thakur, Shenai and Bui in claim 1 using Xi was within the ordinary ability of one of ordinary skill in the art before the effective filing date of the claimed invention based on the teachings of Xi. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of the combined art of Thakur, Shenai and Bui in claim 1 and Xi to obtain the invention: incorporating a base substrate with its components.
Claim(s) 22-23 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combined art of Thakur, Shenai and Bui in claim 1, in view of Chen et al. (US 20240223185 A1), hereinafter Chen.
Regarding Claim 22, as best understood, the combined art of Thakur, Shenai and Bui in claim 1 discloses the circuit structure according to claim 1, wherein the circuit structure comprises N buffer branches [Thakur; Fig. 4, 422a-422j], wherein N is a positive integer, and N is an even number [Thakur; Fig. 4, there are 10 buffer branches, where N=10 which is a positive integer and an even number];
a control terminal of a first one of the N buffer branches [Thakur; Fig. 4, input of 422a] is connected to the second voltage division output terminal of the second voltage division branch, and when N≥2 [Thakur; Fig. 4, 10 is greater than 2], a control terminal of an (i+1)-th buffer branch of the N buffer branches is electrically connected to an output terminal of an i-th buffer branch the N buffer branches [Thakur; Fig. 4, input terminal of 422b connected to output terminal of 422a, input terminal of 422c connected to output terminal of 422b, etc.], wherein i is an integer ranging from 1 to (N-1);
a control terminal of each of the N buffer branches [Thakur; Fig. 4, input terminal of each of 422a-422j]; and
an output terminal of each of the N buffer branches [Thakur; Fig. 4, output terminal of each of 422a-422j].
The combined art of Thakur, Shenai and Bui in claim 1 does not explicitly disclose wherein each of the N buffer branches comprises a fifth transistor and a sixth transistor, wherein a channel type of the fifth transistor is different from a channel type of the sixth transistor; a gate of the fifth transistor is electrically connected to a gate of the sixth transistor; and a first electrode of the fifth transistor receives the third power signal, a second electrode of the fifth transistor is electrically connected to a first electrode of the sixth transistor, and a second electrode of the sixth transistor receives the fourth power signal.
However, Chen discloses each of the N buffer branches [Fig. 10/11, 630/640] comprises a fifth transistor [MP3/MP4] and a sixth transistor [MN3/MN4], wherein a channel type of the fifth transistor [paragraph 0049; MP3/MP4 are P-type] is different from a channel type of the sixth transistor [paragraph 0049; MN3/MN4 are N-type];
a gate of the fifth transistor [gate of MP3/MP4] is electrically connected to a gate of the sixth transistor [gate of MN3/MN4] as a control terminal of each of the N buffer branches [input terminal of each of 630/640]; and
a first electrode of the fifth transistor [top electrode of MP3/MP4] receives the third power signal [signal from VH], a second electrode of the fifth transistor [bottom electrode of MP3/MP4] is electrically connected to a first electrode of the sixth transistor [top electrode of MN3/MN4] as an output terminal of each of the N buffer branches [output terminal of each of 630/640], and a second electrode of the sixth transistor [bottom electrode of MN3/MN4] receives the fourth power signal [signal from VL].
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to use the invention of Chen in the invention of the combined art of Thakur, Shenai and Bui in claim 1, with the expected benefit of predictable results of an inverter. This method of improving the combined art of Thakur, Shenai and Bui in claim 1 using Chen was within the ordinary ability of one of ordinary skill in the art before the effective filing date of the claimed invention based on the teachings of Chen. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of the combined art of Thakur, Shenai and Bui in claim 1 and Chen to obtain the invention: incorporating internal structure of inverters within the buffers.
Regarding Claim 23, as best understood, the combined art of Thakur, Shenai and Bui in claim 1, in view of Chen, discloses the circuit structure according to claim 1, wherein a width-to-length ratio of a fifth transistor in the (i+1)-th buffer branch is greater than a width-to-length ratio of a fifth transistor in the i-th buffer branch, and/or a width-to-length ratio of a sixth transistor in the (i+1)-th buffer branch is greater than a width-to-length ratio of a sixth transistor in the i-th buffer branch [Chen; paragraph 0049; increasing channel W/L ratio], wherein N≥2 [Thakur; Fig. 4, N=10]; or,
wherein the fifth transistor is a P-type channel transistor [Chen; paragraph 0049; MP3/MP4 are P-type], and the sixth transistor is an N-type channel transistor [Chen; paragraph 0049; MN3/MN4 are N-type].
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Proebsting (US 5926050 A).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Amit Bhatia whose telephone number is (571)272-4410. The examiner can normally be reached Monday-Friday 8:30am-4:30pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Regis Betsch can be reached at (571) 270-7101. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Amit R Bhatia/Examiner, Art Unit 2836
/REGIS J BETSCH/SPE, Art Unit 2836
