DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-6, 8 and 16-18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hupe’ (USP 4,151,429).
Regarding claim 1, Hupe’s figure 1 shows A circuit comprising: an operational amplifier (15) including a first op-amp input (+), a second op-amp input (-), and an op-amp output (OP); a first switch(22) connected between the first op-amp input (+) and a supply node (V); a second switch (23) connected between the second op-amp input (-)and the supply node (V); a first capacitor (18) connected between the first op-amp input (+) and a ground node (ground potential); a second capacitor (19) connected to the second op-amp input (-); a third switch (25) connected between the second capacitor and a sample input (VR2); and a fourth switch (20) connected between the second capacitor and the op-amp output (OP) as called for in claim 1.
Regarding claim 2, Hupe’s circuit is configured to perform a sample and hold operation on the sample input.
Regarding claim 3, Hupe’s circuit is inherently capable of sample and hold operation holds a sample input voltage on the op-amp output for greater than 100 milliseconds.
Regarding claim 4, Hupe’s circuit inherently sample and hold operation includes a sample phase and a hold phase, wherein a length of the hold phase greater than 500 times a length of the sample phase.
Regarding claims 5 and 17, wherein during the sample phase, the first switch is closed (22), the second switch (23) is closed, the third switch (25) is closed, and the fourth switch (20) is open, and wherein during the hold phase, the first switch is open (22), the second switch (23) is open, the third switch (25) is open, and the fourth switch (20) is closed (see figure 2 for waveforms that operates first to fourth switches).
Regarding claim 6, Hupe’s figure 1 shows the sample phase and the hold phase are defined by a clock signal, and the first switch, the second switch, the third switch, and the fourth switch are configured to receive gate control signals (figure 2) that are defined based on the clock signal (the gate control signals are inherently defined based on a clock signal).
Regarding claim 8, wherein the first capacitor and the second capacitor are matched with approximately a same capacitance.
Regarding claim 16, the methods comprising steps that are fully anticipated by Hupe’s figure 1, thus, claim 16 is also rejected under 35USC 102(a)(1).
Regarding claim 18, wherein the sample phase and the hold phase are defined by a clock signal, wherein the hold phase holds a sample input voltage on the op-amp output for greater than 100 milliseconds and wherein a length of the hold phase greater than 500 times a length of the sample phase (see figure 2).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hupe’ (USP 4,151,429) in view of shigehara (USP 6,194,952).
Regarding claims 7 and 19, Hupe’s figure 1 shows an apparatus comprising all the aspects of the present invention except the first switch and second switch are both PMOS transistors that each include a source connection to the supply node and a bulk connection to the supply node as called for in claims 7 and 19. However, one skilled in the art would have recognized that NMOS and PMOS transistors are complementary transistors, thus, interchanging of one type for the other will not alter the circuit operation. Therefore, it would have been obvious to person skilled in the art before the effective filing date of the invention to replace Hupe’s NMOS transistors with PMOS transistors because they are functionally equivalent.
Regarding the limitation of having a bulk connection of PMOS transistor coupled to the supply node, it is also well known in the art when a PMOS is built in a n-type substrate, there p-n junctions between the n-type body and the p-type source/drain region. If the body is at a lower voltage than the source, these junction can become forward-biased, allowing leakage current and potentially turning the transistor on unintentionally. Therefore, by connecting the back-gate or bulk to the highest supply voltage, these junctions remain reverse-biased, thus, minimizing leakage current and keep the transistor in a controlled state. This is also demonstrated by Shigehar’s figure 2E which shows PMOS’s bulk connected to a power supply. Therefore, outside of any non-obvious results, the obviousness of having a PMOS transistor bulk connected to a power supply will not be patentable under 35USC 103.
Claim(s) 9, 13-15 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hupe’ (USP 4,151,429) in view of Pereira et al. (US 2006/0119501).
Regarding claim 9, Hupe’s figure 1 shows a circuit comprising all the aspects of the present invention as noted above including the circuit comprises a first sample and hold circuit but does not show a first reference voltage of a bandgap and a second sample and hold circuit for a second reference voltage of the bandgap, wherein the second sample and hold circuit includes the same or similar elements as the first sample and hold circuit as called for in claim 9.
Pereira et al.’s figure 5A shows multiples similar sample and hold circuits (220, 230) each receives a bandgap reference voltage. Therefore, it would have been obvious to person skilled in the art before the effective filing date of the invention to include multiple sample and hold circuits and bandgap reference voltage in Hupe’s circuit arrangement as taught by Pereira et al. reference to form a bigger system.
Regarding claim 13, Hupe’s figure 1 shows a circuit comprising all the aspects of the present invention as noted above except a voltage generator circuit is configured to generate a voltage during a sample phase, and wherein the voltage generator circuit is disabled during a hold phase as called for in claim 13.
Pereira et al. reference shows a reference voltage circuit (212) coupled to a sample and hold circuit. One skilled in the art would have recognized that in order to reduce power consumption, one would have disabled the reference voltage circuit when the sample and hold circuit is in a holding phase since the reference voltage is no longer needed. Therefore, outside of any non-obvious results, the obviousness of having the reference voltage circuit disable during the holding phase in order to reduce power consumption will not be patentable under 35USC.
Regarding claims 14, and 20 Hupe’s figure 1 shows a circuit comprising all the aspects of the present invention as noted above including the circuit comprises a first sample and hold circuit but does not show a first reference voltage of a bandgap generator and a second sample and hold circuit for a second reference voltage of the bandgap generator, wherein the second sample and hold circuit includes the same or similar elements as the first sample and hold circuit as called for in claims 14 and 20.
Pereira et al.’s figure 5A shows multiples similar sample and hold circuits (220, 230) each receives a bandgap reference voltage. Therefore, it would have been obvious to person skilled in the art before the effective filing date of the invention to include multiple sample and hold circuits and bandgap reference voltage in Hupe’s circuit arrangement as taught by Pereira et al. reference to form a bigger system.
Regarding claim 15, the voltage generator circuit is configured to generate a voltage reference that is temperature-dependent (circuit components are temperature dependent).
Claim(s) 10-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hupe’ (USP 4,151,429) in view of Nagda et al. (US 2014/0145691).
Regarding claims 10-11, Hupe’s figure 1shows a sample and hold circuit comprising all the aspects of the present invention as noted above except for the operational amplifier is further connected to another circuit/multiplier circuit (claim11), wherein the circuit is configured to use the operational amplifier during a sample phase of the sample and hold operation, and the another circuit is configured to use the operational amplifier during a hold phase of the sample and hold operation as called for in claims 10-11.
Nagda et al.’s figure 1 shows a sample and hold circuit (112 and 122) coupled to a multiplier circuit (106) to form a tracking voltage. Therefore, it would have obvious to person skilled in the art before the effective filing date of the invention to include Nagda’s multiplier circuit in Hupe’s circuit arrangement to form a tracking voltage circuit as taught by Nagda reference.
Allowable Subject Matter
Claim 12 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art of record, Hupe reference does not teach or fairly suggest the operational amplifier comprises a two-stage operational amplifier, wherein the sample and hold circuit and the multiplier circuit each comprise a first stage of the two-stage operational amplifier and wherein the sample and hold circuit is configured to use a second stage of the operational amplifier during the sample phase of the sample and hold operation and the multiplier circuit is configured to use the second stage of the operational amplifier during the hold phase of the sample and hold operation as called for in claim 12.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. In this regard, White (USP 5,258,664) discloses a sample and hold circuit comprising an operational amplifier (42), first switch (34), second switch (35), first capacitor (40), second capacitor (C5), third and fourth switches (45).
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/TUAN T LAM/Primary Examiner, Art Unit 2836 8/3/2026
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