DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-7 and 9-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhou (US 11569806) in view of Moraveji (US 6937071).
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With respect to claim 1, fig. 5, 6 and 7 of Zhou discloses an inverter-based comparator (210), comprising: an output stage circuit (610 and 710) including a P-type output transistor (712 or 612) and an N-type output transistor (618 and 718) electrically connected in series in an order from a first supply voltage (640 or 740) to a second supply voltage (642/742) being lower than the first supply voltage, and electrically connected at an output node (604 or 704) that provides an output voltage; a first inverter (512 shown in detail in fig. 6) having a first transition voltage with an input node coupled to an input voltage (at output of 530) and an output node generating a first inverted voltage (at output of 512) and coupled to a gate of the N-type output transistor; and a second inverter (514) having a second transition voltage with an input node coupled to the input voltage (at output of 530) and an output node generating a second inverted voltage (at output of 514) and coupled to a gate of the P-type output transistor, the second transition voltage being greater than the first transition voltage, the first inverter (512) and the second inverter (514) each including an inverter that comprises: a first inverter branch (630 and 730 respectively) composed of at least one first P-type transistor (632 and 734) and at least one first N-type transistor (634 or 638 (col. 10 lines 4-5) and 736 (col. 13 line 26) or 738 are NMOS transistors); and a second inverter branch (620 and 720) composed of at least one second P-type transistor (622 and 724), at least one second N-type transistor (624 or 628 (col. 9 lines 26-27) and 726 (col. 13 line 66) or 728 are NMOS transistors) and at least two tuning switches (626, 628 and 722, 728 respectively); wherein the first inverter branch and the second inverter branch are configured to compare the input voltage (602 and 702) with an internal trigger point (at 706, 708, 606, and 608) thereby generating a compare voltage as an inverted voltage of the first inverter (512) or the second inverter (514) at an interconnected node; and one of the at least two tuning switches is controlled to isolate the first supply voltage (640) and another is controlled to isolate the second supply voltage (742) to generate the first transition voltage or the second transition voltage but fails to disclose a resistor electrically connected between the first supply voltage and the output stage circuit but fails to disclose wherein the first inverted voltage and the second inverted voltage independently drive the N-type output transistor and the P-type output transistor respectively of the same output stage circuit.
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It is well known to use a resistor to decrease a supplied voltage to a desired voltage level. See for example fig. 1 of Moraveji disclosing R1 lowering the voltage at the gate of 111. It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to use a resistor (as shown in Moraveji) to decrease the voltage level at 227 to a precise voltage level desired with a resistor for the purpose or obtaining the desired voltage level.
It is well known in the art to separate parts of an invention. (See In re Dulberg, 289 F.2d 522, 523, 129 USPQ 348, 349 (CCPA 1961) (The claimed structure, a lipstick holder with a removable cap, was fully met by the prior art except that in the prior art the cap is "press fitted" and therefore not manually removable. The court held that "if it were considered desirable for any reason to obtain access to the end of [the prior art’s] holder to which the cap is applied, it would be obvious to make the cap removable for that purpose."). As the inverters produce the same signals driving the same output stage using independent N-type output transistors and P-type outputV transistors is obvious in view of the circuits above.
With respect to claim 2, Zhou discloses the comparator of claim 1, wherein the second inverter branch is coupled to receive at least one tuning signal (706 and 708 control tuning switches 732, 722 and 712 and 738, 728 and 718) for controlling the at least two tuning switches. (Here, the control of the tuning switches are not limited to controlling the switches inside the branch.)
With respect to claim 3, Zhou discloses the comparator of claim 1, wherein the at least one first P-type transistor (i.e. 622) and the at least one first N-type transistor (i.e. 624) are electrically connected in series in an order from the first supply voltage (640) to the second supply voltage (642/742), gates of the at least one first P-type transistor and the at least one first N-type transistor are coupled to the input voltage (from 530 at 602), and the interconnected node electrically coupled between the at least one first P-type transistor (i.e. 622) and the at least one first N-type transistor (i.e. 624) provides the compare voltage. ((Here, the duty cycle of the output voltage provided from 210 is the basis for comparison by 220) (col. 17 lines 37-49) “In one example, the DCM circuitry 220 determines the duty cycle of the output signal and compares the duty cycle to the desired duty cycle percentage.”) (Note: Here 642 and 742 are considered ground reference voltage.)
With respect to claim 4, Zhou discloses the comparator of claim 1, wherein the at least one second P-type transistor (i.e. 632) and the at least one second N-type transistor (i.e. 634) are electrically connected in series in the order from the first supply voltage (640) to the second supply voltage (642/742), gates of the at least one second P-type transistor and the at least one second N-type transistor are coupled to the input voltage (at 602), and the at least one second P-type transistor and the at least one second N-type transistor are electrically coupled at the interconnected node. (Note: Here 642 and 742 are considered ground reference voltage.)
With respect to claim 5, Zhou discloses the comparator of claim 1, wherein the at least two tuning switches comprise: a top switch (i.e. 636, 626) connected between the first supply voltage (640) and the at least one second P-type transistor (i.e. 632, 622) or between the interconnected node and the at least one second P-type transistor; and a bottom switch (i.e. 638, 628)connected between the second supply voltage (642/742) and the at least one second N-type transistor (i.e. 634, 624) or between the interconnected node and the at least one second N-type transistor.
With respect to claim 6, Zhou discloses the comparator of claim 1, wherein the at least two tuning switches comprise: two top switches (i.e. 636, 626) respectively connected between the first supply voltage (640) and the at least one second P-type transistor (632 or 622) and between the interconnected node (602) and the at least one second P-type transistor (632 or 622); and two bottom switches (638 and 628) respectively connected between the second supply voltage (642/742) and the at least one second N-type transistor (634 or 624) and between the interconnected node (602) and the at least one second N-type transistor (634 or 624).
With respect to claim 7, Zhou discloses the comparator of claim 1, wherein the inverter further comprising a third inverter branch (i.e. 620 of 522, 720 of 524) composed of at least one third P-type transistor (622), at least one third N-type transistor (624) and at least two tuning switches (i.e. 626 and 628); wherein the at least one first P-type transistor (632 and 734) comprises series-connected first P-type transistors (626 and 622, 722, 724), the at least one first N-type transistor 634 or 638 (col. 10 lines 4-5) and 736 (col. 13 line 26) or 738 are NMOS transistors) comprises series- connected first N-type transistors (i.e. 624, 628, 726, 728), the at least one second P-type transistor ((622 and 724),) comprises series-connected second P-type transistors (622, 626,722, 724), the at least one second N- type transistor comprises series-connected second N-type transistors (624, 628, 726,728)), the at least one third P-type transistor comprises series-connected third P-type transistors (626 and 622), or the at least one third N-type transistor comprises series-connected third N- type transistors (624,628).
With respect to claim 9, Zhou discloses an inverter-based comparator (210) powered between a first supply voltage (640) and a second supply voltage (642/742) being lower than the first supply voltage, the comparator comprising: a first inverter (512) having a first transition voltage with an input node coupled to an input voltage (output from 530) and an output node generating a first inverted voltage (at output of 512); a second inverter (514) having a second transition voltage with an input node coupled to the input voltage (output from 530) and an output node generating a second inverted voltage (at output of 514), the second transition voltage being greater than the first transition voltage; and an inverter (522) composed of: a first inverter branch (630) composed of at least one first P-type transistor (632) coupled to the second inverted voltage (output at 514) and at least one first N-type transistor (634) coupled to the first inverted voltage (output at 512); and a second inverter branch (620) composed of at least one second P-type transistor (622) coupled to the second inverted voltage (output of 514), at least one second N-type transistor (624) coupled to the first inverted voltage (output of 512) and at least two tuning switches (626 and 628); wherein the first inverter branch (630) and the second inverter branch (620) are configured to compare the first inverted voltage (output of 512) and the second inverted voltage (output of 514) with an internal trigger point, thereby generating a compare voltage as an output voltage (output of 210) at an interconnected node; and one of the at least two tuning switches is (636 or 626) controlled to isolate the first supply voltage (640) and another (638,or 628) is controlled to isolate the second supply voltage (642/742) to compensate for trigger point shifting but fails to disclose a resistor electrically connected between the first supply voltage and the output stage circuit.
It is well known to use a resistor to decrease a supplied voltage to a desired voltage level. See for example fig. 1 of Moraveji disclosing R1 lowering the voltage at the gate of 111. It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to use a resistor (as shown in Moraveji) to decrease the voltage level at 227 to a precise voltage level desired with a resistor for the purpose or obtaining the desired voltage level.
With respect to claim 10, Zhou discloses the comparator of claim 9, wherein the second inverter branch (620) is coupled to receive at least one tuning signal (606) for controlling the at least two tuning switches (636 and 626).
With respect to claim 11, Zhou discloses the comparator of claim 9, wherein the at least one first P-type transistor (632) and the at least one first N-type transistor (634) are electrically connected in series in an order from the first supply voltage (640) to the second supply voltage (642/742), gates of the at least one first P-type transistor and the at least one first N-type transistor are coupled to the second inverted voltage (at 602 output of 514) and the first inverted voltage (at 602 output of 512) respectively, and the interconnected node (at 602) electrically coupled between the at least one first P-type transistor (632) and the at least one first N-type transistor (634) provides the compare voltage.
With respect to claim 12, Zhou discloses the comparator of claim 9, wherein the at least one second P-type transistor (622) and the at least one second N-type transistor (624) are electrically connected in series in the order from the first supply voltage (640) to the second supply voltage (642/742), gates of the at least one second P-type transistor (622) and the at least one second N-type transistor (624) are coupled to the second inverted voltage (at output of 514) and the first inverted voltage ( at output of 512) respectively, and the at least one second P-type transistor and the at least one second N-type transistor are electrically coupled at the interconnected node (602).
With respect to claim 13, Zhou discloses the comparator of claim 9, wherein the at least two tuning switches (636 and 638) comprise: a top switch (636) connected between the first supply voltage (640) and the at least one second P-type transistor (632) or between the interconnected node and the at least one second P-type transistor; and a bottom switch (638) connected between the second supply voltage (642/742) and the at least one second N-type transistor (634) or between the interconnected node and the at least one second N-type transistor.
With respect to claim 14, Zhou discloses the comparator of claim 9, wherein the at least two tuning switches (626 and 628) comprise: two top switches (626 and 636) respectively connected between the first supply voltage (640) and the at least one second P-type transistor (622) and between the interconnected node (602) and the at least one second P-type transistor (622); and two bottom switches (628 and 638) respectively connected between the second supply voltage (642/742) and the at least one second N-type transistor (624) and between the interconnected node (602) and the at least one second N-type transistor(624).
With respect to claim 15, Zhou discloses the comparator of claim 9, wherein the inverter further comprising a third inverter branch (i.e. 620 of 522, 720 of 524) composed of at least one third P-type transistor (622),, at least one third N-type transistor (624) and at least two tuning switches i.e. 626 and 628) ;wherein the at least one first P-type transistor (632) comprises series-connected first P-type transistors (626 and 622),, the at least one first N-type transistor (transistor 634 or 638 (col. 10 lines 4-5) comprises series- connected first N-type transistors (634 and 638) , the at least one second P-type transistor (622) comprises series-connected second P-type transistors ((622 and 626),, the at least one second N- type transistor (624) comprises series-connected second N-type transistors (624, 628,) the at least one third P-type transistor comprises series-connected third P-type transistors (626 and 622),, or the at least one third N-type transistor comprises series-connected third N- type transistors(624,628)..
Response to Arguments
Applicant's arguments filed 5/26/2026 have been fully considered but they are not persuasive.
Frist with respect to applicant’s argument that the prior art fails to disclose “wherein the first inverted voltage and the second inverted voltage independently drive the N-type output transistor and the P-type output transistor respectively of the same output stage circuit.”, the Examiner agrees, however this would be an obvious design choice.
Applicant argues that the structural difference is not a design choice, the Examiner disagrees. Applicant argues the difference would produce a predictable hysteresis window. The Examiner points out as the claimed invention does not focus on the beneficial attributes of the design window or power and only focuses on the separation of the drivers, the benefits of the hysteresis is not implicated in the claim language nor the beneficial aspects of power. As such this is merely a design choice as the separation of the components would fully encapsulate the claimed invention.
With respect to applicant’s argument concerning Zhou, the applicant argues the fundamental structural deficiency in Zhou (i.e. lack of a shared output stage), remains unaddressed, the Examiner disagrees. Zhou’s output stage was disclosed as being (610 and 710) which is eventually produces the single output at 204. As such the rejection was addressed and should be maintained.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAREEM E ALMO whose telephone number is (571)272-5524. The examiner can normally be reached M-F (8:00am-4:00pm).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at (571)-270-36 M-F (8:00am-4:00pm). The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KHAREEM E ALMO/Examiner, Art Unit 2849
/Menatoallah Youssef/SPE, Art Unit 2836
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