DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 2, 12, 15, 17, and 18 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 13-14 of U.S. Patent No. 11,296,706. Although the claims at issue are not identical, they are not patentably distinct from each other because, despite the claim recitations are merely reworded to recite the same limitation in different language and some of the limitations have been grouped in a slightly different manner, the instant claims are broader than and thus anticipated by the patent claims.
For example: reworded “sector” is the same limitation as “region” in the patent claims.
Claims 1, 12, and 17, the elements and the limitations are anticipated by the patent claims 13-14.
Claim 2, the elements and the limitations are anticipated by patent claim 14.
Claim 15, the elements and the limitations are anticipated by patent claim 14.
Claim 18, the elements and the limitations are anticipated by patent claim 14 (wherein the first region of the region-aligned memory is connected to a first region of the plurality of regions of programmable logic fabric via the physical connection; …. wherein the second region of the region-aligned memory is connected to a second region of the plurality of regions of programmable logic fabric via an additional physical connection distinct from the physical connection…).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 10, and 12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chow et al. (US 8,719,753).
Claim 1, Chow discloses a system (Figs 1A-1B, 2, 5-6) comprising:
a first die (FPGA Die Layer, Figs. 2 or 5) comprising a plurality of sectors (col. 7, lines 57-67,… The FPGA die layer may be partitioned into 2.sup.N segments, where N is 2 or larger. The FPGA die layer may be partitioned into 4, 8, 16, 32, or more segments…) and configurable to operate on data; and
a second die comprising a network on chip (NOC) circuitry (NoC Die Layer, Fig. 2) configurable to route data between each sector of the plurality of sectors (see Fig.2, blocks with dotted line box, Fig. 2 or blocks with dotted line box, Fig. 5 are segments connected to Non-blocking Interconnect Switches for routing signals/data among the segments) of the first die, wherein the first die and second die coupled in a stacked configuration (see Figs. 1A-1B).
Claim 10, Chow discloses the system of claim 1, wherein the second die (NoC Die Layer, Fig. 5) comprises a plurality of memory interfaces (multiple DMA 511 on Noc Die Layer, Fig. 5) and configurable to route data between off-package memory (external memory interface is for coupling to an External Memory that is connected to one of the DMA 511, see Fig. 5).
Claim 12 is rejected as above claim 1 because the elements and limitations are similar.
Allowable Subject Matter
Claims 3-9, 11, 13-14, 16, 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Swarbrick et al. (US 2019/0363717) discloses a system comprising: a first die comprising a plurality of regions and configurable to operate on data; and a second die comprising a network on chip (NOC) circuitry configurable to route data between each sector of the plurality of region of the first die, wherein the first die and second die coupled in a stacked configuration.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANH Q TRAN whose telephone number is (571)272-1813. The examiner can normally be reached M-F: 9AM - 5PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander H Taningco can be reached at 571-272-8048. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ANH Q TRAN/Primary Examiner, Art Unit 2844 12/10/25