Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
2. This is a final action on the merits in response to the reply received 12/29/2025.
Response to Arguments
Applicant’s arguments have been considered but are not persuasive.
Applicant argues that Chiba disclosure is irrelevant to the claimed limitation. The examiner respectfully disagrees. Chiba discloses encoding information of at least one block that has been encoded to determine the optimization level of the current block because the number of sub-areas on which the encoding process is to be performed is also reduced, thereby reducing a capacity of a memory required to retain the result of counting the number of valid coefficients of each sub-area of the block in [0049]. Rejection is maintained.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3 are rejected under 35 U.S.C. 102A1 as being anticipated by US 20030194145 A1-Chiba et al (Hereinafter referred to as “Chiba”).
Regarding claim 1, Chiba discloses an encoder,(fig. 1) comprising:
a quantization circuit (Fig. 1, element 4), configured to perform a quantization operation on multiple blocks of current frame data in sequence, to generate multiple quantized data respectively corresponding to the multiple blocks ([0016], quantized multiple coefficients);
a quantized data adjustment circuit ([0019], adjusting section), wherein for each of the multiple blocks in the current frame data, the quantized data adjustment circuit adjusts multiple coefficients in the quantized data corresponding to the block according to an optimization level of the block, to generate adjusted quantized data ([0044], wherein adjusting quantization coefficients of the multiple blocks in accordance with a degree of appearance of valid coefficients. The degree of appearance of valid coefficients are interpreted as an optimization level); and
an encoding circuit (Fig. 1), configured to encode the adjusted quantized data of each of the multiple blocks to generate encoded data ([0044], encoding the adjusted quantized coefficients).
an optimization level calculation circuit, wherein for a current ([0049], wherin block that has not been encoded by the encoding circuit, the optimization level calculation circuit refers to encoding information of at least one block that has been encoded to determine the optimization level of the current block( [0049], wherein perform the encoding processes can be vastly reduced, while grasping features of the source image at the same time. Further, the number of sub-areas on which the encoding process is to be performed is also reduced, thereby reducing a capacity of a memory required to retain the result of counting the number of valid coefficients of each sub-area, which contributes to saving memory. This is interpreted as optimization).
Regarding claim 3, Chiba discloses the encoder of claim 1, wherein the encoding information of the at least one block that has been encoded comprises an optimization level ([0049], wherein perform the encoding processes can be vastly reduced, while grasping features of the source image at the same time. Further, the number of sub-areas on which the encoding process is to be performed is also reduced, thereby reducing a capacity of a memory required to retain the result of counting the number of valid coefficients of each sub-area, which contributes to saving memory. This is interpreted as optimization) and a bit number of the encoded data corresponding to the at least one block ([0087], bit number).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4, 8 are rejected under 35 U.S.C. 103 as being unpatentable over US 20030194145 A1-Chiba et al (Hereinafter referred to as “Chiba”), in view of US 20090232225 A1-Yang et al (Hereinafter referred to as “Yang”).
Regarding claim 4, Chiba discloses the encoder of claim 3 (See claim 3),
Chiba fails to disclose wherein the optimization level calculation circuit calculates a predicted bit number of encoded data of the current block according to the bit number of the encoded data of the at least one block that has been encoded; and the optimization level calculation circuit determines the optimization level of the current block according to the predicted bit number of the encoded data of the current block, a target bit number of the current block, a total number of bits that can be lent, and the optimization level of the at least one block.
However, in the same field of endeavor, Yang discloses wherein the optimization level calculation circuit calculates a predicted bit number of encoded data of the current block according to the bit number of the encoded data of the at least one block that has been encoded ([0059]); and the optimization level calculation circuit determines the optimization level of the current block according to the predicted bit number of the encoded data of the current block, a target bit number of the current block, a total number of bits that can be lent, and the optimization level of the at least one block ([0059]).
Therefore, it would have been obvious to one of ordinary skilled in the art before the effective filing date of the claimed invention to modify the imaging optical system disclosed by Chiba to disclose wherein the optimization level calculation circuit calculates a predicted bit number of encoded data of the current block according to the bit number of the encoded data of the at least one block that has been encoded; and the optimization level calculation circuit determines the optimization level of the current block according to the predicted bit number of the encoded data of the current block, a target bit number of the current block, a total number of bits that can be lent, and the optimization level of the at least one block as taught by Yang, to improve optimization performance ([0039], Yang)
Regarding claim 8, Chiba discloses the encoder of claim 1 (See claim 1),
Chiba fails to disclose a quantization parameter calculation circuit, configured to determine a quantization parameter of the current frame data according to a target bit number of the current frame data and encoding and/or quantization information of previous frame data, for the quantization circuit to perform the quantization operation on the multiple blocks of the current frame data in sequence.
However, in the same field of endeavor, Yang discloses a quantization parameter calculation circuit (Fig. 3), configured to determine a quantization parameter of the current frame data according to a target bit number of the current frame data ([0059], wherein determining the appropriate QP based on the target bit) and encoding and/or quantization information of previous frame data (Fig 3), for the quantization circuit to perform the quantization operation on the multiple blocks of the current frame data in sequence ([0071], quantization).
Therefore, it would have been obvious to one of ordinary skilled in the art before the effective filing date of the claimed invention to modify the imaging optical system disclosed by Chiba to disclose a quantization parameter calculation circuit, configured to determine a quantization parameter of the current frame data according to a target bit number of the current frame data and encoding and/or quantization information of previous frame data, for the quantization circuit to perform the quantization operation on the multiple blocks of the current frame data in sequence as taught by Yang, to improve optimization performance ([0039], Yang).
Allowable Subject Matter
Claims 5-7, 9-12, 14-16 allowed.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LERON BECK whose telephone number is (571)270-1175. The examiner can normally be reached M-F 8 am-5pm.
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LERON . BECK
Examiner
Art Unit 2487
/LERON BECK/ Primary Examiner, Art Unit 2487