DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-10 and 21-30 are pending in the application.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. 15/345790, filed on 08 November 2016.
Information Disclosure Statement
Acknowledgment is made of applicant’s Information Disclosure Statement(s) (IDS), Form PTO-1449, filed 07 August 2024. The information therein was considered.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 22-30 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 12-20 of U.S. Patent No. 11,296,114 (‘114). Although the claims at issue are not identical, they are not patentably distinct from each other because the limitations of the instant application are recited in the claims of ‘114 with only nominal differences that would have been obvious to one of ordinary skill in the art.
Allowable Subject Matter
Claims 1-10 and 21 are allowed.
Claims 22-30 would be allowable if the double patenting rejection set forth in this Office action is overcome.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art of record fails to teach the claimed limitations in combination namely, as recited in independent claim 1, a non-volatile memory device comprising: a semiconductor substrate; a driving circuit provided on the semiconductor substrate; control gate electrode films spaced apart from each other in a first direction, the control gate electrode films and the driving circuit being arranged in the first direction; a selection gate electrode film provided between the driving circuit and the control gate electrode films in the first direction, the selection gate electrode film being divided into plural parts each extending in a second direction perpendicular to the first direction, the plural parts being alternately arranged with isolating portions in a third direction perpendicular to the first direction and the second direction and being electrically isolated each other in the third direction, the isolating portions including a first isolating portion and a second isolating portion arranged in the third direction, a width of the second isolating portion in the third direction being smaller than a width of the first isolating portion in the third direction; a first semiconductor body piercing through the control gate electrode films and a first part of the plural parts of the selection gate electrode film in the first direction, the first semiconductor body forming first memory cells at crossing portions with the control gate electrode films and forming a first selection transistor at a crossing portion with the first part of the selection gate electrode film; a second semiconductor body piercing through the control gate electrode films and the first part of the selection gate electrode film in the first direction, the second semiconductor body forming second memory cells at crossing portions with the control gate electrode films and forming a second selection transistor at a crossing portion with the first part of the selection gate electrode film, the first and second semiconductor bodies being arranged in a direction perpendicular to the first direction and oblique to the third direction; a third semiconductor body piercing through the control gate electrode films and a second part of the plural parts of the selection gate electrode film in the first direction, the third semiconductor body forming third memory cells at crossing portions with the control gate electrode films and forming a third selection transistor at a crossing portion with the second part of the selection gate electrode film; a fourth semiconductor body piercing through the control gate electrode films and the second part of the selection gate electrode film in the first direction, the fourth semiconductor body forming fourth memory cells at crossing portions with the control gate electrode films and forming a fourth selection transistor at a crossing portion with the second part of the selection gate electrode film, the third and fourth semiconductor bodies being arranged in a direction perpendicular to the first direction and oblique to the third direction; the first part of the selection gate electrode film surrounds an outer periphery of the first semiconductor body and an outer periphery of the second semiconductor body wholly when viewed from the first direction, a portion of the first part of the selection gate electrode film surrounding the outer periphery of the first semiconductor body and a portion of the first part of the selection gate electrode film surrounding the outer periphery of the second semiconductor body being formed as one body; and the second part of the selection gate electrode film surrounds an outer periphery of the third semiconductor body and an outer periphery of the fourth semiconductor body wholly when viewed from the first direction, a portion of the second part of the selection gate electrode film surrounding the outer periphery of the third semiconductor body and a portion of the second part of the selection gate electrode film surrounding the outer periphery of the fourth semiconductor body being formed as one body; and as recited in independent claim 22, a non-volatile memory device comprising: a substrate; an insulation film provided above the substrate; a first conductive layer provided above the insulation film; an upper interconnect structure including a first interconnection; first electrode films provided between the first conductive layer and the upper interconnect structure, the first electrode films being arranged in a first direction perpendicular to the first conductive layer; a second electrode film provided between the first conductive layer and the first electrode films in the first direction; at least one semiconductor body extending through the first electrode films and the second electrode film in the first direction, and forming memory cells at crossing portions with the first electrode films and forming a selection transistor at a crossing portion with the second electrode film, one end of the semiconductor body being electrically connected to the first conductive layer, and the other end of the semiconductor body being electrically connected to the first interconnection; and an isolating portion extending through the first electrode films and the second electrode film in the first direction and in a second direction perpendicular to the first direction and dividing the first electrode films and the second electrode film in a third direction perpendicular to the first direction and the second direction, the isolating portion including silicon ad germanium and a side wall insulating film.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chen US 2015/0206896 teaches a 3D memory device including selection lines, bit lines and cells arranged in a plurality of rows and columns, wherein a column direction is parallel to the bit lines while a row direction is parallel to the selection lines. The adjacent cells in the same column are electrically connected to the different bit lines.
Arai US 2016/0240552 teaches a memory device including a stacked body with interconnect portions penetrating the stacked body and a back gate and extending in the X-direction and the Z-direction.
Konagai et al. US 9,935,121 teach a memory device including an insulating film extending along the Z-direction and the Y-direction within an insulating layer, a stacked body and a back gate electrode film.
Tsuji et al. US 10,283,525 teach a memory device including a conductive body extending through stacked electrodes in the Z-direction, wherein the conductive body includes a first portion and a second portion and the width of the second portion in the X-direction is wider than a width of the first portion in the X-direction.
The examiner has cited particular columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. When responding to this office action, applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALLISON BERNSTEIN whose telephone number is (571)272-9011. The examiner can normally be reached M-F 8AM-5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached on 571-272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ALLISON BERNSTEIN/Primary Examiner, Art Unit 2824 10/9/2026
Prosecution Insights