DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings received on 08/08/2024 have been accepted by the examiner.
Information Disclosure Statement
Acknowledgment is made of applicant's Information Disclosure Statement (IDS) Form PTO-1449, filed 08/08/2024 & 09/01/2025. The information disclosed therein was considered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3 & 12-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Grunzke et al (US20120233433) in view of Choy et al (US9741435).
Regarding claim 1, Grunzke discloses a storage device comprising (FIG 3; [0025-0026]); a plurality of memory package chips each including a plurality of memory dies capable of storing data(330-1 to 330-N); and a controller configured to communicate with the plurality of memory package chips (FIG; 315 in communication with 330-1 to 300-N) and connected to the plurality of memory package chips through one or more daisy chain circuits (FIG 3; [0026] 330-1 to 330-N arranged in a daisy chain configuration with chip signals CEs), and the point being connected to a first daisy chain circuit of the one or more daisy chain circuits(point on 320 line connected to 330-1 -330-N), and wherein the controller is coupled to the point (the point on 320 line is connected to 315)
However, Grunzke does not disclose an input capacitor connected between a point and a ground, the point being connected to a first daisy chain circuit of the one or more daisy chain circuits, and wherein the controller is coupled to the point.
In the same field of endeavor, Choy an input capacitor connected between a point and a ground (FIG 1-2; 215 connected between a 217 and a ground Vss).
Grunzke and Choy are analogous art because they are all directed to a memory device comprising memory array with switches, and one of ordinary skill in the art would have had a reasonable expectation of success by modify Grunzke to include Choy because they are from the same field of endeavor.
Therefore, it would be obvious to include the teachings of Choy in the teachings of Grunzke for the benefits improving voltage sampling done by the capacitor during phases of a memory operation e.g., controlling rising time in phase 1 in FIG 4 (col 9, line 63 – col 10-line 3 Choy).
Regarding claim 2, Grunzke discloses wherein each of the plurality of memory package chips further includes an interface chip connected to the plurality of memory dies and configured to provide an interface for the controller to access the plurality of memory dies (FIG 3; [0027] 330-1 and 330-N connected to 328-1 and 328-2 chip signals CE).
Regarding claim 3, Grunzke discloses wherein the memory dies included in one of the memory package chips are divided into a first memory die group and a second memory die group FIG 3; 330-1
comprising 313-1 and 313-2 and 330-N comprising 313-3 and 313-P), wherein the memory dies included in the first memory die group are connected to the interface chip through a first channel (FIG 3; 313-1
connected to CE1), and wherein the memory dies included in the second memory die group are connected to the interface chip through a second channel (FIG 3; 313-P connected to CE2).
Regarding claim 12, Grunzke discloses the point between the controller and another point where a conductive line branches from the first daisy chain circuit to a memory package chip closest to the controller among the plurality of memory package chips(FIG 3; line 320 point and another point below 330-1_330-N connected to plurality of 330-1-330-N and controller 315) , the input capacitor is connected between 1) the point between the controller and another point where a conductive line, and 2) the ground (Choy FIG 1-2; 215 connected between a 217 and a ground Vss, and other lines).
Regarding claim 13, Grunzke discloses wherein the first daisy chain circuit is connected to an address latch enable signal terminal, a command latch enable signal terminal, a write enable signal terminal, or a chip enable signal terminal of the controller (FIG 3; 315 comprising chip enable signal CE connected to first daisy chain circuit).
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Grunzke et al (US20120233433) in view of Choy et al (US9741435) further in view of Bernardi et al (US20090043932)
Regarding claim 4, Grunzke discloses one or more of the daisy chain circuits (FIG 3).
However, Grunzke does not disclose further comprising a termination resistor connected to one
or more of the daisy chain circuits.
In the same field of endeavor, Bernardi discloses further comprising a termination resistor
connected to one or more of the daisy chain circuits (FIG 4; [0062] FIG 4; discloses a resistor 450 chip
packages 420, 430 and 440 in common signal line 410, Further FIG 9, teaches multi chips packages
devices 910,920 and 930 connected to a common signal line in daisy chain circuits and it can obvious to
modify FIG 4 of resistor 450 to FIG 9 in daisy chain circuits).
Grunzke in view of Choy and Bernardi are analogous art because they are all directed to chip packaging devices connected in daisy chain connection and one of ordinary skill in the art would have had a reasonable expectation of success by modify Grunzke in view of Choy to include Bernardi because they are from the same field of endeavor.
Therefore, it would be obvious to include the teachings of Bernardi (having a resistor connected
to daisy chain connection) in the teachings Grunzke in view of Choy for the benefits allowing the common sharing signal line in daisy chain can be driven to a potential close to GND to prevent receiving dominant value at the common sign line that may cause a value that is different from the value output to the common signal line by the receivers) ([0059 and 0063] Bernardi).
Allowable Subject Matter
Claims 5-11 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Schoch et al (US20020188781 FIG 2; discloses hips devices in daisy-chain configuration with controller 10).
Aulagnier et al (US20210175806 FIG 3a; [0014] discloses daisy-chain configuration for chips devices and also comprising controller).
Wentzloff et al (US20150382296 FIG 8a; capacitor, resistors and ground).
McCarthy et al (US778057 FIG 4-5; discloses chips devices in daisy-chain configuration).
Park et al (US20040037133 FIG 2B-2C; discloses chips devices in daisy-chain configuration).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUNA A TECHANE whose telephone number is (571)272-7856. The examiner can normally be reached 571-272-7856.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached on 571-272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MUNA A TECHANE/ Primary Examiner, Art Unit 2827