Prosecution Insights
Last updated: October 23, 2026
Application No. 18/797,575

METHOD FOR PRODUCING SEMICONDUCTOR COMPONENTS FROM A WAFER USING A CARRIER WAFER

Non-Final OA §103§112
Filed
Aug 08, 2024
Priority
Sep 04, 2023 — DE 10 2023 208 478.3
Examiner
PUNCHBEDDELL, SEYON ALI-SIMAH
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Robert Bosch GmbH
OA Round
1 (Non-Final)
77%
Grant Probability
Favorable
1-2
OA Rounds
1y 3m
Est. Remaining
87%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allowance Rate
71 granted / 92 resolved
+9.2% vs TC avg
Moderate +10% lift
Without
With
+10.0%
Interview Lift
resolved cases with interview
Typical timeline
3y 5m
Avg Prosecution
33 currently pending
Career history
129
Total Applications
across all art units

Statute-Specific Performance

§103
55.7%
+15.7% vs TC avg
§102
27.7%
-12.3% vs TC avg
§112
15.5%
-24.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 92 resolved cases

Office Action

§103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 3 and 4 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 3 recites the limitation "to provide openings in the filler material" in line. There is insufficient antecedent basis for this limitation in the claim. Claim 4 is rejected due to claim 3 dependency. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1, 6 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over as applied to claim above, in view of Tseng et al. (US 20240339370 A1; hereinafter “Tseng”) in view of Hiner et al. (US 9653428 B1; hereinafter “Hiner”). In regard to claim 1, Tseng teaches a method for producing semiconductor components (packages 80′) including power semiconductor components (device dies 10) (Fig. 1, Fig. 14 and paragraph 12 and 57), from a wafer (a carrier 52 with release film 54) (Fig. 8 and paragraph 35), comprising the following steps: providing a wafer substrate (a semiconductor substrate 101) (Fig. 5E and paragraph 36); processing a structured wafer surface (a redistribution structure 56) (Fig. 9 and paragraph 36); applying a carrier wafer (a portion that functions as the carrier wafer is shown annotated as CW in annotated Fig. 11 below) onto the wafer substrate (annotated Fig. 2 and paragraphs 28 and 32); and wherein the carrier wafer is applied to the wafer surface using a dam-and-fill process step (as encapsulant 66 fills the gaps between neighboring metal posts 62 and the gaps between metal posts 62 composite die 50’, therefore the carrier wafer CW is formed using a dam-and-fill process) (Fig. 9-11 and paragraphs 39-42). PNG media_image1.png 547 815 media_image1.png Greyscale Tseng doesn’t explicitly teach reducing a thickness of the wafer substrate by wafer thinning. Hiner teaches a thickness of a wafer substrate (carrier 621) by wafer thinning (the carrier can be removed by utilizing chemical-mechanical planarization (CMP)) (Fig. 6F-2, [col 29, lns 39-45]). It would have been obvious to one skilled in the art to combine the teachings of Tseng with the teachings of Hiner to have a thickness of the wafer substrate by wafer thinning since CMP is a known method of removing carriers from wafers. In regard to claim 6, Tseng teaches wherein the applying of the carrier wafer includes applying an organic or inorganic ink and subsequent curing (the encapsulant formed of SiO2 is deposited and then cured) (Fig. 11 and paragraph 47). In regard to claim 11, Tseng teaches a semiconductor component (packages 80′) (Fig. 14, produced by: providing a wafer substrate (a semiconductor substrate 101) (Fig. 5E and paragraph 36); processing a structured wafer surface (a redistribution structure 56) (Fig. 9 and paragraph 36); applying a carrier wafer (a portion that functions as the carrier wafer is shown annotated as CW in annotated Fig. 11 below) onto the wafer substrate (annotated Fig. 2 and paragraphs 28 and 32); and wherein the carrier wafer is applied to the wafer surface using a dam-and-fill process step (as encapsulant 66 fills the gaps between neighboring metal posts 62 and the gaps between metal posts 62 composite die 50’, therefore the carrier wafer CW is formed using a dam-and-fill process) (Fig. 9-11 and paragraphs 39-42). Allowable Subject Matter Claims 2, 5, and 7-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. In regard to claim 2, Tseng is considered a close prior art of reference. However, Tseng fails to teach wherein the dam-and-fill process step includes applying at least one frame structure to the wafer surface using digital printing technology and filling a volume delimited by the frame structure with a filler material by dispensing the filler material. Tseng teaches the elements that form the frame is formed through an etching process. In regard to claim 5, Tseng is considered a close prior art of reference. However, Tseng fails to teach wherein the method includes selectively removing filler material, using a laser. Tseng does not teach the method of laser etching nor teaches an embodiment where laser etching could be applied. In regard to claim 7, Tseng is considered a close prior art of reference. However, Tseng fails to teach wherein the applying of the carrier wafer includes multiple dam-and-fill process steps for applying multiple superimposed layers, which are applied sequentially and with respective subsequent curing. Tseng teaches the curing occurs in one step. In regard to claim 8, Tseng is considered a close prior art of reference. However, Tseng fails to teach wherein a frame structure and/or a filler material is applied to an outer rounded region of the wafer substrate in the dam-and-fill process step in such a way that a rounded region is evened out and made level with a surface of the wafer substrate. Tseng is silent regarding an outer rounded region of the wafer substrate. In regard to claim 9, Tseng fails to teach Tseng is considered a close prior art of reference. However, Tseng fails to teach the method includes applying a support layer which is water-soluble and laterally delimited by a frame structure to the wafer surface, by digital printing technology, prior to applying a filler material of the carrier wafer. Tseng fails to teach the use of multiple support layers that are removed. Claim 10 is objected to due to depending on claim 9. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Lee et al. (US 2022/0021179 A1). Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEYON ALI-SIMAH PUNCHBEDDELL whose telephone number is (571)270-0078. The examiner can normally be reached Mon-Thur: 7:30AM-3:30 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at (571) 272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SEYON ALI-SIMAH PUNCHBEDDELL/Examiner, Art Unit 2893 /SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Aug 08, 2024
Application Filed
Oct 02, 2026
Non-Final Rejection mailed — §103, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12772637
DISPLAY PANEL AND DISPLAY DEVICE
3y 1m to grant Granted Oct 20, 2026
Patent 12764213
Patterning in Devices with Organic Light-Emitting Diode Displays and Sensors
4y 1m to grant Granted Oct 13, 2026
Patent 12751169
DISPLAY DEVICE HAVING A FIRST LAYER AND A SIGNAL WIRE HAVING DIFFERENT THICKNESSES
4y 1m to grant Granted Sep 29, 2026
Patent 12751145
DISPLAY DEVICE
3y 3m to grant Granted Sep 29, 2026
Patent 12751175
DISPLAY DEVICE WITH A RIB HAVING A PARTITION WITH A CONDUCTIVE PORTION AND MANUFACTURING METHOD THEREOF
3y 5m to grant Granted Sep 29, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
77%
Grant Probability
87%
With Interview (+10.0%)
3y 5m (~1y 3m remaining)
Median Time to Grant
Low
PTA Risk
Based on 92 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month