Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-7 remain pending in the application under prosecution and have been examined.
In the response to this Office action, the Examiner respectfully requests that support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line numbers in the specification and/or drawing figure(s). This will assist the Examiner in prosecuting this application.
Examiner cites particular columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in Korea on Foreign Application 10-2023-0110453. It is noted, however, that applicant has not filed a certified copy of the Korean application as required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-7 are rejected under 35 U.S.C. 103 as being unpatentable over US 20230115936 (POLISI et al) in view of US 6,360,327 (HOBSON).
With respect to claim 1, POLISI teaches integrated circuit device comprising: a memory configured to store trim data therein (integrated circuits (ICs) including configuration data stored in non-volatile memory (NVM) for trimming one or more circuit); a sleep register configured to input the trim data to a sleep function block (plurality of configuration registers within the integrated circuit, causing the integrated circuit to transition into a standby state with content of the plurality of configuration registers is preserved by a first voltage) [Par. 0156-0158]; a normal register configured to input the trim data to a normal function block (during normal operation, (e.g., upon power up of the IC) the stored trimmed configuration is data is copied from the non-volatile memory to the plurality of configuration registers) [Par. 0007; Par. 0156-0158]; a memory controller configured to load the trim stored in the memory into the sleep register or the normal register (main control circuit to enable the configuration data being copied from the embedded memory to the plurality of configuration registers, after the configuration data is copied from the embedded non-volatile memory to the plurality of configuration registers, cause the integrated circuit to transition into a standby state) [Par. 0156; Par. 0024-0025; Par. 0007-0009]; and a wake controller configured to load the trim data stored in the normal register into the sleep register via the memory controller upon first self-wake-up after power-up so as to allow the memory to be loaded first-time only after the power-up (upon reception of a wakeup event, cause the configuration data from the plurality of configuration registers to be copied to the volatile memory, and cause the integrated circuit to transition into an active state in and the circuit to operate based on the configuration data stored in the volatile memory) [Par. 0156; Par. 0024-0025; Par. 0007-0009].
POLISI fails to specifically teach a sleep register disposed in an always-on power domain and configured to input the trim data to a sleep function block, a normal register disposed in a normal-power domain and configured to input the trim data to a normal function block, and wherein the sleep register and the normal register are physically distinct registers. However, HOBSON teaches (power management system in a computer system utilizing control registers including): a sleep register disposed in an always-on power domain (a sleep register with sleep type bits transmitted to the sleep register configured to allow the computer system to remain in fully operational mode) and configured to input the trim data to a sleep function block (true sleep type bits to the sleep register to place the computer system into sleep mode), a normal register disposed in a normal-power domain and configured to input the trim data to a normal function block (a decoy register with bit state so that the computer system retain normal operating mode) and wherein the sleep register and the normal register are physically distinct registers (the bit value of the sleep register to enter sleep mode and the bit value of the decoy register in the normal operating mode being different values) [Abstract; Fig. 4; Col. Col. 6, Lines 1-31; Col. 14, Line 56 to Col. 15, Line 14] . Therefore it would have been obvious to one having at least ordinary skill in the art before the effective filing of the instant application to modify the stored trimmed configuration data, taught by POLISI, by implementing the sleep register and normal (decoy) register, as taught by HOBSON, in order to implement actual status used for power management functions for hardware-based power management systems requiring special configuration sequences, as taught by HOBSON [Col. 12, Lines 31-58].
With respect to claim 2, POLISI and HOBSON, combined, teach integrated circuit device, wherein the wake controller is configured to, upon receipt of a stabilization completion signal from the sleep function block upon power-up, power up the memory, the memory controller, the normal register, and the normal function block
(registers storing several monitoring or result signals or flags for the integrated system wakeup sequence, once completed or indication of pass signal, allowing stability or restore values implemented in the system power state) [POLOSI’s Par. 0053-0056; Par. 0068-0069; Par. 0043-0044];
(controller defining pawer state indicating normal function and sleep function registers) [HOBSON’s Col. 12, Line 59 to Col. 13, Line 19].
With respect to claim 3, POLISI and HOBSON, combined, teach integrated circuit device, wherein the memory controller is configured to load the trim data into the sleep register and the normal register, and load the trim data stored in the normal register into the sleep register prior to entering a low-power mode
(loading of the configuration data, wherein the IC transitions into a low power state in which the content of the configuration registers is preserved) [POLOSI’s Par. 0024-0025].
(controller defining pawer state indicating normal function and sleep function registers and the computer transitioning to the power mode defined by the PM1a sleep type bits with the operating system writing to the PM1a and PM1b registers to the sleep register; after configuring the peripheral devices, transferring the contents of the decoy register (PM1b ) including the true sleep code, into the sleep register (PM1a )) [HOBSON’s Col. 6, Lines 1-27, Lines 46-59; Col. 12, Line 59 to Col. 13, Line 19].
With respect to claim 4, POLISI and HOBSON, combined, teach integrated circuit device, wherein the memory is configured to retain the trim data even upon power-off
(configuration registers maintaining data content stored through low energy, i.e., upon interruption of the external power supply) [POLOSI’s Par. 0024-0025];
(setting power management function retaining data even when power is off) [HOBSON’s Col. 2, Lines 1-18] .
With respect to claim 5, POLISI and HOBSON, combined, teach integrated circuit device, wherein the memory controller is configured to, upon external wake-up after self-wake-up, load the trim data stored in the sleep register into the normal register ([0074] wakeup event causing the exiting of standby state after the assertion of signal WAKE_ON to operates as a transition state to normal state) [POLOSI’s Par. 0074-0075; Par. 0035-0038].
With respect to claim 6, POLISI and HOBSON, combined, teach integrated circuit device, wherein the sleep register is configured to retain the trim data during the supply of always-on power
(content of the plurality of configuration registers is preserved by the first voltage, and when the integrated circuit is in the standby state) [POLOSI’s Par. 0064; Par. 0008-0009]
(configuring the peripheral devices transferring the contents of the decoy register (PM1b ) including the true sleep code, into the sleep register (PM1a ) that controls the ACPI power states of the computer system based on the sleep type code (i.e., the sleep type bits) stored in the sleep register) [HOBSON’s Col. 6, Lines 46-59].
With respect to claim 7, POLISI and HOBSON, combined, teach integrated circuit device, wherein the normal register is configured to retain the trim data during the supply of always-on power and normal power
(main logic continues to receive power in standby state preserving the content of configuration registers during standby state) [POLOSI’s Par. 0063-0064]
(configuring the peripheral devices transferring the contents of the decoy register (PM1b ) including the true sleep code, into the sleep register (PM1a ) that controls the ACPI power states of the computer system based on the sleep type code (i.e., the sleep type bits) stored in the sleep register) [HOBSON’s Col. 6, Lines 46-59].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 5878264 A (EBRAHIM) teaching power sequence controller containing wakeup logic for responding to each wakeup event signal intercepted by the power sequence controller, the wakeup logic to compare the intercepted wakeup event signal with a wakeup filter mask to determine if the wakeup event signal should be processed or ignored.
US 20070028080 A1 (HOBSON et al).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PIERRE MICHEL BATAILLE whose telephone number is (571)272-4178. The examiner can normally be reached Monday - Thursday 7-6 ET.
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/PIERRE MICHEL BATAILLE/Primary Examiner, Art Unit 2136