Detailed Action
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This application is a continuation of U.S. Patent Application No. 17/847,131, filed June 22, 2022, now U. S. Patent No. 12,086,064 B2, issued Sep.10, 2024, which is a continuation of U.S. Patent Application No. 16/882,344, filed May 22, 2020, now U. S. Patent No. 11,392,498, issued July 19, 2022, which claims priority to U.S. Provisional Patent Application No. 62/852,461, filed May 24, 2019. Claims 1, 5, 13 and 17 are amended, no claims have been cancelled, claims 1-20 are pending for examination.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Response to applicant’s Arguments
Applicant’s arguments, see page 6-7, filed 11/17/2025, with respect to the rejection(s) of claim(s) 1, 9, 12-13 and 19-20 under 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Gathala et al., US 2015/0046661 A1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 9, 12-13 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over MIZUNO et al., US 2017/0123835 A1, in view of Campbell et al., US 2020/0250099 A1, further in view of Gathala et al., US 2015/0046661 A1.
Regarding claims 1 and 13, MIZUNO teaches an apparatus comprising:
a memory including a first portion and a second portion (section 0064; The hypervisor 101 allocates a region used by the hypervisor 101 and a region used by the virtual server 102 on the memory 103);
at least one register (section 0057; a memory management unit 202 that manages the switching notifying unit 203) configured to:
indicate respective ownership of the first portion and the second portion to a processor core (section 0065; when a physical address (a host memory address) is allocated as illustrated in FIG. 3, the hypervisor 101 allocates addresses AD0 and AD1 to the region of the hypervisor 101, allocates addresses AD1 and AD2 to the virtual server 102-1, allocates addresses AD3 and AD4 to the virtual server 102-2, and allocates addresses AD3 and AD4 to the shared data region 218 used when the virtual server 102-1 and the virtual server 102-2 perform communication using the shared memory); and
a controller (the hypervisor 101) coupled to the memory and the at least one register (Fig.2).
MIZUNO does not clearly teach at least one register configured to indicate whether the memory operates in an aliased mode or an un-aliased mode, direct the first memory access instruction and the second memory access instruction to the memory based on the indication of the at least one register.
However, Campbell teaches at least one register configured to indicate whether the memory operates in an aliased mode or an un-aliased mode (see abstract: determining whether the alias tag valid bit is set in the corresponding entry of the virtual cache; in response to the alias tag valid bit not being set, determining whether the virtual cache data access demand is a synonym of the corresponding entry in the virtual cache; and in response to the virtual access demand being a synonym of the corresponding entry in the virtual cache with the same virtual address but a different context tag, updating information in a tagged entry in an alias table), direct the first memory access instruction and the second memory access instruction to the memory based on the indication of the at least one register (section 0025; the two processes can have the same virtual address mapping to different physical addresses, otherwise referred to as homonyms).
It would have been obvious to the ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Campbell into MIZUNO's memory system such as at least one register configured to indicate whether the memory operates in an aliased mode or an un-aliased mode, direct the first memory access instruction and the second memory access instruction to the memory based on the indication of the at least one register because it increases processor performance by permitting multiple processes or threads to hit concurrently in a virtual cache if they have the same virtual address, same physical address, but different context tags (section 0074 of Campbell).
MIZUNO and Campbell do not clearly teach receiving memory access instructions directed to the same virtual address from different processor cores.
However, Gathala teaches receiving memory access instructions directed to the same virtual address from different processor cores (sections 0036-0039; assigning the same virtual address in different processors).
It would have been obvious to the ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Gathala into MIZUNO and Campbell's memory system such as receiving memory access instructions directed to the same virtual address from different processor cores because it allows the processors to avoid performing address translation operations and more directly communicate pointers, relative addresses, virtual addresses or via references to the shared memory. The various aspects reduce the number of operations that are performed when offloading portions of a general purpose software application to an auxiliary processor, thereby improving the performance characteristics of the mobile device. The various aspects also reduce the amount of information that is communicated via system buses and fabrics, further improving the performance characteristics of the device (section 0039 of Gathala).
Regarding claims 9 and 19, MIZUNO teaches the first memory access instruction and the second memory access instruction are respectively a write instruction and a read instruction (section 0051; a hypervisor 101 is loaded onto the memory 103, and a-guest OS 111 is operated through the virtual server 102 controlled by the hypervisor 101); and the first value indicates that the first processor core is associated with the first portion of the memory (claim 1; generating the communication path between the first virtual machine and the second virtual machine by associating a region of the memory referred to by the first virtual machine and a region of the memory referred to by the second virtual machine).
Regarding claims 12 and 20, MIZUNO teaches a first level (L1) cache (it is taught as buffer 215) and a second level (L2) cache, wherein the memory is the L2 cache (Fig.2; it is taught as memory 103).
Allowable Subject Matter
Claims 2-8, 10-11 and 14-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance:
The limitations not found in the prior art of record include the at least one register is configured to indicate a first value or a second value, wherein the first value indicates that the first processor core owns the first portion of the memory and the second processor core owns the second portion of the memory, and wherein the second value indicates that the first processor core owns the second portion of the memory and the second processor core owns the first portion of the memory in combination with the other claimed limitations as described in the claims 2 and 14 (claims 3-8 and 15-18 are depended on claims 2 and 14 respectively).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The limitations not found in the prior art of record include first virtual address is associated with the first portion of the memory, and wherein the controller is configured to generate an indication of an error based on that the virtual address is associated with a physical address outside an address range of the first portion in combination with the other claimed limitations as described in the claim 10 (claim 11 is depended on claim 10).
When responding to the office action, Applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present in view of the state of the art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections. See 37 C.F.R. 1.111 (c).
When responding to the office action, Applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist examiner to locate the appropriate paragraphs.
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/HUA J SONG/Primary Examiner, Art Unit 2133