DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 8-15 and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over JOO et al. 20230187380 in view of DOANY et al. 20150063755.
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Regarding claim 1, figs. 8-9 of JOO discloses a semiconductor package, comprising:
an interposer 700 that extends in a first direction (across the page – X) and comprises a plurality of lower pads and a plurality of upper pads;
a first semiconductor chip 100 on the interposer, wherein the first semiconductor chip comprises a first side portion (left side vertical surface portion) and a second side portion (right side vertical surface portion) that extend in parallel with a second direction (into the page – Y) that is perpendicular to the first direction,
wherein the first semiconductor chip 100 comprises a first physical layer 101 (fig. 2) in a first region (region of 101) of the first semiconductor chip that is adjacent to the first side portion and a second physical layer 1010 in a second region (region of 110) of the first semiconductor chip that is adjacent to the second side portion;
a integrated circuit (IC) chip 200A comprising a plurality of first through vias 220 (fig. 8) that at least partially overlap the second region of the first semiconductor chip in a third direction (vertical direction – Z) perpendicular to the first direction and the second direction,
wherein a first portion of the IC chip is on the first semiconductor chip; and
an electronic IC chip 200B on the IC chip 200A, wherein the electronic IC chip 200B comprises a third physical layer 201 (fig. 8) that at least partially overlaps the second region of the first semiconductor chip in the third direction.
JOO does not discloses that the integrated circuit (IC) chip 200A is a photonic integrated circuit (IC) chip.
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However, par [0073] of DOANY discloses FIGS. 14A-C illustrate an exemplary embodiment for coupling light in plane between a multicore fiber 102 and three-dimensional chip stack 135, each chip 136 containing one or more optical waveguides 103. This is based on single-mode multicore fibers 102 and on semiconductor chips with single-mode optical waveguides 103. An exemplary embodiment uses a stack of Silicon photonic chips with optical waveguides. In exemplary embodiments, Silicon photonic chips can be manufactured using semiconductor-on-insulator (SOI) substrates and CMOS processes.
Note Chip can be Photonic chip stack.
As such it would have been obvious to form a package of JOO wherein the integrated circuit (IC) chip 200A is a photonic integrated circuit (IC) chip such as taught by DOANY in order to form package having photonic chip in order for coupling light.
Regarding claim 11 (see rejection of claim 1 above), JOO and DOANY discloses a semiconductor package, comprising:
an interposer 700 that extends in a first direction and comprises a plurality of lower pads and a plurality of upper pads;
a first semiconductor chip 100 on the interposer, wherein the first semiconductor chip comprises a first side portion and a second side portion that extends in parallel with a second direction that is perpendicular to the first direction, wherein the first semiconductor chip comprises a first physical layer in a first region of the first semiconductor chip that is adjacent to the first side portion and a second physical layer in a second region of the first semiconductor chip that is adjacent to the second side portion (see rejection of claim 1 above); a photonic IC chip comprising a plurality of first through vias that at least partially overlap the second region of the first semiconductor chip in a third direction perpendicular to the first direction and the second direction, wherein a first portion of the photonic IC chip is on the first semiconductor chip;
and a second semiconductor chip 200B comprising a fourth physical layer that at least partially overlaps the first region of the first semiconductor chip in the third direction, wherein a second portion of the second semiconductor chip is on the first semiconductor chip.
Regarding claims 2 and 12, fig. 14 of DOANY discloses further comprising: an optical fiber array unit 102 on the photonic IC chip and comprising a plurality of optical fibers.
As such it would have been obvious to form a package further comprising: an optical fiber array unit 102 on the photonic IC chip and comprising a plurality of optical fibers in order to transmit light.
Regarding claims 3 and 13, fig. 9A of DOANY discloses wherein the photonic IC chip comprises an optical waveguide 128 configured to transmit an optical signal received from the plurality of optical fibers 102 and an optical element 128 configured to convert the optical signal into an electrical signal.
As such it would have been obvious to form a package further comprising: an optical fiber array unit 102 on the photonic IC chip and comprising a plurality of optical fibers in order process transmit light.
Regarding claims 4 and 14, fig. 8 of JOO discloses further comprising: a second semiconductor chip 200C (an electronic IC chip 200C on the photonic IC chip) comprising a fourth physical layer that at least partially overlaps the first region of the first semiconductor chip in the third direction, wherein a second portion of the second semiconductor chip is on the first semiconductor chip.
Regarding claim 5, fig. 8 of JOO discloses further comprising: a plurality of a third semiconductor chip 200D on the second semiconductor chip, wherein the second semiconductor chip comprises a plurality of second through vias 220 and
Furthermore, it would have been obvious to form a plurality of third semiconductor chip instead of a single third semiconductor as adding more chips on top another is not inventive and can be done to meet the applicant design.
Regarding claim 8, figs. 8-9 of JOO discloses further comprising: a plurality of molding members 710/250/240 that are on the interposer and at least partially overlap the first semiconductor chip, the photonic IC chip, and the electronic IC chip in the first direction.
Regarding claim 9, fig. 8 of JOO discloses wherein the first semiconductor chip comprises a plurality of second through vias 220 in the first region of the first semiconductor chip and the second region of the first semiconductor chip.
Regarding claim 10, fig. 9 of JOO discloses further comprising: a plurality of conductive connection members 720 that are respectively on the plurality of lower pads 705 of the interposer.
Regarding claim 14, fig. 9 of JOO discloses further comprising: an electronic IC chip 200C on the photonic IC chip.
Regarding claim 15 (see rejection of claim 5) further comprising: a plurality of third semiconductor chips on the second semiconductor chip, wherein the second semiconductor chip comprises a plurality of third through vias, and wherein the electronic IC chip comprises a third physical layer that at least partially overlaps the second region of the first semiconductor chip in the third direction (fig. 8).
Regarding claim 18, figs. 8-9 of JOO discloses wherein the first semiconductor chip comprises a plurality of second through vias in the first region and the second region.
Regarding claim 19, fig. 9 of JOO further comprising: a plurality of conductive connection members that are respectively on the plurality of lower pads 705 of the interposer.
Allowable Subject Matter
Claims 6-7 and 16-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 20 is allowed. JOO discloses all the limitations of claim 20 except for “a first die that is on the interposer and is spaced apart from the first semiconductor chip, wherein a first protruding portion of the photonic IC chip that extends from the first semiconductor chip is on the first die; and a second die that is on the interposer and is spaced apart from the first semiconductor chip, wherein a second protruding portion of the second semiconductor chip that extends from the first semiconductor chip is on the second die”.
Conclusion
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/VONGSAVANH SENGDARA/Primary Examiner, Art Unit 2893
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