Prosecution Insights
Last updated: October 27, 2026
Application No. 18/798,206

OVERLAY NETWORK LOOP DETECTION AND PREVENTION

Non-Final OA §103
Filed
Aug 08, 2024
Examiner
RECEK, JASON D
Art Unit
2458
Tech Center
2400 — Computer Networks
Assignee
Cisco Technology Inc.
OA Round
3 (Non-Final)
71%
Grant Probability
Favorable
3-4
OA Rounds
1y 3m
Est. Remaining
93%
With Interview

Examiner Intelligence

Grants 71% — above average
71%
Career Allowance Rate
529 granted / 746 resolved
+12.9% vs TC avg
Strong +22% interview lift
Without
With
+22.1%
Interview Lift
resolved cases with interview
Typical timeline
3y 6m
Avg Prosecution
27 currently pending
Career history
780
Total Applications
across all art units

Statute-Specific Performance

§101
10.5%
-29.5% vs TC avg
§103
55.6%
+15.6% vs TC avg
§102
12.9%
-27.1% vs TC avg
§112
13.9%
-26.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 746 resolved cases

Office Action

§103
DETAILED ACTION This is in response to the RCE filed on July 7th 2026. Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 7/7/26 has been entered. Response to Arguments Applicant’s arguments, see pg. 10, filed 7/7/26, with respect to the claim objection have been fully considered and are persuasive. The objection of claim 7 has been withdrawn. Applicant’s arguments, see pg. 10, with respect to the 112 rejection have been fully considered and are persuasive. The 112 rejection of claims 1-20 has been withdrawn. Applicant’s arguments, see pg. 10-14, with respect to the rejection(s) of claim(s) 1-20 under 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Pani et al. US 9,444,634 B2. Claim Rejections - 35 USC § 103 The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action. Claim(s) 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Brar et al. US 2023/0283549 A1 in view of Pani et al. US 9,444,634 B2. Regarding claim 1, Brar discloses: performing a loop detection in order to detect a loop among multiple networked entities (method for network loop prevention by applying a loop detection protocol – title, abstract, paragraph 4; multiple loop detection “techniques” – see paragraphs 4-6; paragraph 159 explicitly discloses a variety of known STP flavors that may be used; thus they system is multiple), the multiple network entities comprising a fabric overlay network (overly/virtual network – paragraphs 5, 41, 55, 58, Fig. 1), a first external data link layer switch, and a second external data link layer switch (multiple layer 2 switches – paragraphs 5, 35 and Figs. 2-3; regarding the word “external”, applicant points to Figs. 6-8 and states everything is part of the same cloud/network and therefore “internal”; however, claims are interpreted under the BRI, the claims do not define what “external” is in reference to, so the switches may be part of the logical network, but are still physically and literally “external” to one of the networked entities; therefore, the switches of Brar read on “external” under the BRI), wherein the first external data link layer switch and the second external data link layer switch are coupled externally of the fabric overlay network (switches are coupled via physical network 218, see Fig. 2, which is external to the overlay/virtual network “VCN” – see Figs. 1, 2 and 6), wherein the loop enables forwarding network packets in multiple redundant traverse of the fabric overlay network, the first external data link layer switch, and the second external data link layer switch (this is simply the definition of a network loop – see paragraphs 35 and 157 which teaches link layer switches may suffer from looping issues; also see “loop” – paragraph 169, Fig. 9); wherein performing loop detection comprises: providing, by at least one fabric edge component of the fabric overlay network, detection information to … the fabric overlay network, the detection information comprising first detecting information associated with the first external data link layer switch and second detection information associated with the second external data link layer switch (network has edge components – paragraph 135, Fig. 5; forward loop detection information, e.g. MAC address data, BPDU, etc. – see abstract, paragraphs 4-5, 9, 34-35, 159, 184-186 and Figs. 10-15); and detecting … the loop based on the detection information provided by the at least one fabric edge component (detect loop - see abstract, paragraphs 4-5, 9, 34-35, 159, 184-186 and Figs. 10-15); in response to detecting the loop, modifying … at least one fabric edge component of the fabric overly network to disable the loop, wherein modifying comprises reconfiguring the at least one fabric edge component to block network packets communicated between the fabric edge and the first external data link layer switch (update edge component with loop prevention rule – paragraphs 68, 175-176, Figs. 10, 14, the rule prevents/blocks packets from being sent to the switch – paragraphs 179, 188). Brar does not explicitly disclose providing detection information to at least one fabric controller or detecting the loop by the at least one fabric controller (Brar teaches the NVD implements the loop detection/prevention, see paragraph 189). However, this is taught by Pani as a network loop detection system that sends detection information (MCP packet) using one or more switches that are “external” and then a physical device (i.e. controller) makes a loop detection and subsequent modification (see abstract, col. 3 ln. 33-50, col. 12 ln. 25-40 and Figs. 3, 6, 9). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Brar with the teachings of Pani for improving loop detection. Pani teaches the problems loops prevent (e.g. “fatal meltdown”) and thus provides clear motivation for preventing and detecting loops (see col. 2 ln. 24-50, 4 ln. 26-29 and col. 6 ln. 4-22). Regarding claim 2, Brar discloses, detection information comprises spanning tree topology information, and wherein the fabric network overlay … is configured to detect the loop based on the spanning tree topology information (use spanning tree protocol which includes a topology, and provides loop detection/prevention – paragraph 159). Brar does not explicitly disclose a controller detecting the loop but this is taught by Pani as discussed above. The motivation to combine is the same. Regarding claim 3, Brar discloses the spanning tree topology comprises a bridge identifier associated with the fabric edge component (this is simply a standard feature of STP, the bridge ID is part of spanning tree protocol and is exchanged via BDPUs – see paragraph 189) and a virtual local area network identifier associated with the fabric edge component (overlay includes VLAN – paragraph 5, which have identifiers/tags – paragraph 128). Regarding claim 4, Brar discloses the fabric overlay network … is adapted to detect the loop based on the spanning tree topology information by comparing the spanning tree topology information with other spanning tree topology information received from another fabric edge component of the fabric overlay network (detect loop based on received BPDUs which are part of spanning tree protocol – paragraphs 9, 159 and 184). Brar does not explicitly disclose a controller detecting the loop but this is taught by Pani as discussed above. The motivation to combine is the same. Regarding claim 5, Brar discloses wherein the at least one fabric overlay network … is adapted to reconfigured the at least one fabric edge component to block the network packets communicated between the fabric edge component and the first external data link layer switch by blocking a port of the at least one fabric edge component (disable port on edge component to prevent loop – paragraphs 6, 34, 183). Brar does not explicitly disclose a controller detecting the loop but this is taught by Pani as discussed above. The motivation to combine is the same. Regarding claim 6, Brar discloses wherein the detection information comprises bridge protocol data unit information and wherein the at least one fabric overly network (L2 bridge protocol data unit is part of loop detection – see abstract; transmit BPDU – paragraph 9; control plane is part of network overlay management – paragraphs 46, 68 and Fig. 16), and wherein the network is configured to detect the loop based on a comparison of the bridge protocol data unit information with other bridge protocol data unit information received from at least one other fabric edge component (control plane detects loops based on received BPDUs (paragraphs 9, 184). Brar does not explicitly disclose a controller detecting the loop but this is taught by Pani as discussed above. The motivation to combine is the same. Regarding claim 7, Brar discloses wherein detection information comprises media access control information included in user plane data packets processed by the fabric edge component and at least one other fabric edge component (detect loop based on MAC address – paragraphs 5, 9, 183). Regarding claim 8, Brar discloses the first external data link layer switch and the second external data link layer switch comprise ethernet switches (use Ethernet – paragraph 107). Regarding claim 9, it is a device claim that corresponds to the method of claim 1. Brar discloses a device comprising one or more processors for performing the method (paragraph 237, Fig. 20); therefore the claim is rejected for the same reasons. Regarding claims 10-16, they are device claims that directly correspond to previously presented method claims 2-8; thus, they are rejected for the same reasons. Regarding claim 17, it is a method claim that corresponds to the method of claim 1, the corresponding limitations are rejected for the same reasons. Claim 17 additionally recites a first and second “ethernet” switch instead of the “data link layer” switches recited by claim 1. As explained in the rejection of claim 8, Brar teaches using Ethernet switches (see paragraphs 107, 162). Regarding claims 18-20, they correspond to claims 2 and 6, 7 respectively. Thus, they are also rejected for the same reasons. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Chickering et al. US 2017/0353328 A1 discloses a loop free fabric to detect a loop at a layer 2 network where a control processor blocks external ports (abstract, paragraph 8, Fig. 2). Florit et al. US 2007/0047472 A1 discloses using spanning tree and BPDU to detect and prevent loops (abstract, paragraph 52, Figs. 2-4). Saxena et al. US 2015/0124655 A1 discloses using spanning tree protocol and spanning tree topology to detect and prevent loops in layer 2 networks (abstract, paragraph 4). Gupta et al. US 2013/0003601 A1 discloses an external loop detection method for ethernet switches (abstract, paragraph 29). Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON D RECEK whose telephone number is (571)270-1975. The examiner can normally be reached Flex M-F 9-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Umar Cheema can be reached at 571-270-3037. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JASON D RECEK/Primary Examiner, Art Unit 2458
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Prosecution Timeline

Show 6 earlier events
Apr 21, 2026
Final Rejection mailed — §103
Jun 22, 2026
Interview Requested
Jun 29, 2026
Applicant Interview (Telephonic)
Jun 29, 2026
Examiner Interview Summary
Jul 07, 2026
Request for Continued Examination
Jul 12, 2026
Response after Non-Final Action
Sep 29, 2026
Non-Final Rejection mailed — §103
Oct 14, 2026
Interview Requested

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Prosecution Projections

3-4
Expected OA Rounds
71%
Grant Probability
93%
With Interview (+22.1%)
3y 6m (~1y 3m remaining)
Median Time to Grant
High
PTA Risk
Based on 746 resolved cases by this examiner. Grant probability derived from career allowance rate.

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