DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 12/05/2025 have been fully considered but they are not persuasive.
Specifically, Applicant discusses how “Sun criticizes the prior art embodiment of Figure 2” in Col. 9, lines 38-51. Remarks 12/05/2025, page 9. Based on such discussion, Applicant states that “one of ordinary skill in the art would be discouraged from modifying Sun to include a latch that is serially connected because doing so would limit the signal swing and gain of the circuit, and lead to increased noise and sensitivity to the input common mode voltage.” Id.
Examiner respectfully disagrees. In addition to Applicant’s citations, Sun also teaches in Col. 9, lines 35-36 that “this SA latch design can achieve high speed with one of a positive feedback in the latch phase.” As there is no teaching away in Sun, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the dynamic teachings of Davies, Jr. with the circuitry of Sun et al. for the purpose of utilizing circuitry which “consumes substantially no D.C. power and device threshold sensitivity is virtually eliminated.” Col. 1, lines 25-27.
Thus, all the limitations of the present invention have been taught by the prior art.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-7, 13, 14, 19, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sun et al. (US 11,539,336 B2), in view of Davies, Jr. (4,485,317).
Regarding Claim 1, Sun et al. teaches in Figure 1 a latch comparator, comprising:
a first reservoir capacitor (C RES);
a preamplifier comprising:
first and second transistors respectively connected to first and second inputs (M1, M2), the first and second transistors selectably connectable to a first terminal of the first reservoir capacitor (through 114), and
third and fourth transistors respectively connected to the first and second inputs (M3, M4), the third and fourth transistors selectably connectable to a second terminal of the first reservoir capacitor (through switch controlled by phi amp);
but does not explicitly teach:
a latch, comprising:
a first portion serially connected between the first and third transistors and connected to a first output, and a second portion serially connected between the second and fourth transistors and connected to a second output.
Davies, Jr. teaches an input comparator in Figure 1 comprising:
a latch, comprising:
a first portion serially connected between the first and third transistors and connected to a first output (18 and 24, which connected are between 20 and 26 and connected to node C; see also Figure 3), and
a second portion serially connected between the second and fourth transistors and connected to a second output (30 and 34, which are connected between 32 and 42 and connected to node D; see also Figure 3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the dynamic teachings of Davies, Jr. with the circuitry of Sun et al. for the purpose of utilizing circuitry which “consumes substantially no D.C. power and device threshold sensitivity is virtually eliminated.” Col. 1, lines 25-27.
Regarding Claims 2 and 14, Sun et al. and Davies, Jr., as a whole, teach all the limitations of the present invention, wherein Sun et al. further teaches the latch comparator, wherein the first reservoir capacitor is selectably connectable to a voltage source (using switches controlled by phi int and phi amp signals).
Regarding Claim 3, Sun et al. and Davies, Jr., as a whole, teach all the limitations of the present invention, wherein Sun et al. further teaches the latch comparator, wherein the first, second, third, and fourth transistors are each selectably connectable to one of one or more reset voltages (based on the operation of switches controlled by phi int and phi amp signals).
Regarding Claim 4, Sun et al. and Davies, Jr., as a whole, teach all the limitations of the present invention, wherein Davies, Jr. further teaches the latch comparator,
wherein the first output and the second output are selectably connectable to a common mode voltage (based in part on the operational control of 18, 24, 30, and 34).
Regarding Claim 5, Sun et al. and Davies, Jr., as a whole, teach all the limitations of the present invention, wherein Davies, Jr. further teaches the latch comparator,
wherein the first portion of the latch comprises a first inverter (18 and 24 form a first inverter),
wherein the second portion of the latch comprises a second inverter (30 and 34 form a second inverter), and
wherein the first and second inverters are cross-coupled (where 18, 24, 30, and 34 are configured as cross-coupled inverters; see also Figure 3).
Regarding Claim 6, Sun et al. and Davies, Jr., as a whole, teach all the limitations of the present invention, wherein Sun et al. further teaches the latch comparator, further comprising a controller configured to:
during a reset phase, charge the first reservoir capacitor to a first voltage (when switches connected to C RES are connected to VDD and ground); and
during a comparison phase, connect the first reservoir capacitor to the first, second, third, and fourth transistors (when switches connected to C RES are connected to M1-M4),
wherein the first, second, third, and fourth transistors, and the latch are configured to float during the comparison phase (based on phi int and phi amp control signals).
Regarding Claims 7 and 20, Sun et al. and Davies, Jr., as a whole, teach all the limitations of the present invention, wherein Sun et al. further teaches the latch comparator, wherein the controller is further configured to:
during the reset phase, connect each of the first, second, third, and fourth transistors, and the latch to one of one or more reset voltages (when switches connected to C RES are connected to VDD and ground); and
during the comparison phase, disconnect the first, second, third, and fourth transistors, and the latch from the reset voltage connected thereto in the reset phase (when switches connected to CRES are connected to M1-M4).
Regarding Claim 13, Sun et al. teaches a latch comparator, comprising:
a reservoir capacitor (C RES);
first and second transistors respectively connected to first and second inputs (M1, M2), the first and second transistors selectably connectable to a first terminal of the reservoir capacitor (114);
third and fourth transistors respectively connected to the first and second inputs (M3, M4), the third and fourth transistors selectably connectable to a second terminal of the reservoir capacitor (switch which is controlled by phi amp);
but does not explicitly teach:
fifth and sixth transistors serially connected between the first and third transistors and connected to a first output; and seventh and eighth transistors serially connected between the second and fourth transistors and connected to a second output.
Davies, Jr. teaches an input comparator in Figure 1 comprising:
fifth and sixth transistors serially connected between the first and third transistors and connected to a first output (18 and 24, which connected are between 20 and 26 and connected to node C; see also Figure 3); and
seventh and eighth transistors serially connected between the second and fourth transistors and connected to a second output (30 and 34, which are connected between 32 and 42 and connected to node D; see also Figure 3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the dynamic teachings of Davies, Jr. with the circuitry of Sun et al. for the purpose of utilizing circuitry which “consumes substantially no D.C. power and device threshold sensitivity is virtually eliminated.” Col. 1, lines 25-27.
Regarding Claim 17, Sun et al. and Davies, Jr., as a whole, teach all the limitations, wherein Davies, Jr. further teaches the latch comparator,
wherein the fifth and sixth transistors form a first inverter (18 and 24 form a first inverter),
wherein the seventh and eighth transistors form a second inverter (30 and 34 form a second inverter), and
wherein the first and second inverters are cross-coupled (where 18, 24, 30, and 34 are configured as cross-coupled inverters; see also Figure 3).
Regarding Claim 19, Sun et al. teaches in Figure 4 a method of operating a latch comparator, the method comprising:
during a reset phase, charging a reservoir capacitor to a first voltage (when the switches connected to C RES are connected to VDD and ground); and
during a comparison phase, connecting the reservoir capacitor to first, second, third, and fourth transistors (when the switches connected to C RES are connected to M1-M4),
wherein the first, second, third, and fourth transistors, and a latch are configured to float during the comparison phase (due to the switch configuration of the floating inverter circuit), but does not explicitly teach
wherein at least one of: the first transistor is configured to provide current to the third transistor through the latch, wherein the latch generates a differential output voltage, or the second transistor is configured to provide current to the fourth transistor through the latch, wherein the latch generates a differential output voltage.
Davies, Jr. teaches an input comparator in Figure 1 comprising:
wherein at least one of:
the first transistor is configured to provide current to the third transistor through the latch, wherein the latch generates a differential output voltage (18 and 24, which connected are between 20 and 26 and connected to node C; see also Figure 3), or
the second transistor is configured to provide current to the fourth transistor through the latch, wherein the latch generates a differential output voltage (30 and 34, which are connected between 32 and 42 and connected to node D; see also Figure 3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the dynamic teachings of Davies, Jr. with the circuitry of Sun et al. for the purpose of utilizing circuitry which “consumes substantially no D.C. power and device threshold sensitivity is virtually eliminated.” Col. 1, lines 25-27.
Allowable Subject Matter
Claims 8-12, 15, 16, and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 8, the prior art does not disclose, teach or suggest the latch comparator, further comprising:
fifth and sixth transistors respectively connected to third and fourth inputs, the fifth and sixth transistors selectably connectable to a first terminal of a second reservoir capacitor; and
seventh and eighth transistors respectively connected to the third and fourth inputs, the seventh and eighth transistors selectably connectable to a second terminal of the second reservoir capacitor,
wherein the first portion of the latch is serially connected between the fifth and seventh transistors and connected to a third output, and
wherein the second portion of the latch is serially connected between the sixth and eighth transistors and connected to a fourth output;
in combination with all the other claimed limitations.
Claim 9 is objected to for depending from Claim 8.
Regarding Claim 10, the prior art does not disclose, teach or suggest a data converter, comprising:
a sample and hold circuit connected to the first and second inputs of the latch comparator;
a capacitive digital to analog converter (DAC) connected to the sample and hold circuit; and
a successive approximation register (SAR) logic circuit connected to the capacitive DAC and to the first and second outputs of the latch comparator;
in combination with all the other claimed limitations.
Claims 11 and 12 are objected to for depending from Claim 10.
Regarding Claim 15, the prior art does not disclose, teach or suggest the latch comparator, wherein the first, second, third, and fourth transistors are selectably connectable to a common mode voltage by ninth, tenth, eleventh, and twelfth transistors, respectively;
in combination with all the other claimed limitations.
Regarding Claim 16, the prior art does not disclose, teach or suggest the latch comparator, wherein the first and second outputs are selectably connectable to a common mode voltage by thirteenth and fourteenth transistors, respectively;
in combination with all the other claimed limitations.
Regarding Claim 18, the prior art does not disclose, teach or suggest the latch comparator, further comprising:
ninth and tenth transistors respectively connected to third and fourth inputs, the ninth and tenth transistors selectably connectable to a first terminal of a second reservoir capacitor; and
eleventh and twelfth transistors respectively connected to the third and fourth inputs, the eleventh and twelfth transistors selectably connectable to a second terminal of the second reservoir capacitor,
wherein the fifth and sixth transistors are serially connected between the ninth and eleventh transistors and are connected to a third output, and
wherein the seventh and eighth transistors are serially connected between the tenth and twelfth transistors and are connected to a fourth output;
in combination with all the other claimed limitations.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Contact
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Diana J Cheng whose telephone number is (571)270-1197. The examiner can normally be reached Monday - Friday 9 am - 5:30 pm ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at (571)270-3684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DIANA J. CHENG/Primary Examiner, Art Unit 2849