DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Application
This office action is in response to the Application filed on 08/08/2024.
Claims 1-20 are presented for examination.
Information Disclosure Statement
There was no information disclosure statement (IDS) submitted.
Drawings
The drawings submitted on 08/08/2024 are objected because Figures 1 and 3 contain grayscale drawings that is other than black and white line drawings. Note that, Grayscale drawings, Black and white photographs, including photocopies of photographs, are not ordinarily permitted in utility patent applications. See MPEP 608.02. VII.B. Color photographs and color drawings are not accepted in utility applications unless a petition filed under 37 CFR 1.84{a)(2) is granted. Any such petition must be accompanied by the appropriate fee set forth in 37 CFR 1.17(h), one set of color drawings or color photographs, as appropriate, if submitted via EF S-Web or three sets of color drawings or color photographs, as appropriate, if not submitted via EFS-Web, and, unless already present, an amendment to include the following language as the first paragraph of the brief description of the drawings section of the specification: The patent or application file contains at least one drawing executed in color. Copies of this patent or patent application publication with color drawing(s) will be provided by the Office upon request and payment of the necessary fee. Color photographs will be accepted if the conditions for accepting color drawings and black and white photographs have been satisfied. See 37 CFR 1.84(b)(2). Replacement drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to this Office action. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 103
In the event a determination of the status of the application as subject to AIA 35 U.S.C. 102, 103, and 112 (or as subject to pre-AIA 35 U.S.C. 102, 103, and 112) is incorrect, any correction of the statutory basis for a rejection will not be considered a new ground of rejection if the prior art relied upon and/or the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 7-9, 15 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Cambrian IC (CN 118277305A; hereinafter Cambrian) in view of Maharana et al. (US 2019/0253520; hereinafter Maharana).
Regarding independent claims 1, 15 and 18,taking claim 1 as exemplary analysis, Cambrian teaches A system for data storage in an artificial intelligence (AI) computing environment ([0030], As shown in fig. 1, the board 10 includes a Chip 101, which is a System on Chip (SoC), or a System on Chip, integrated with one or more integrated circuit devices, wherein the integrated circuit device is an artificial intelligence operation unit for supporting various deep learning and machine learning algorithms, and meeting the intelligent processing requirements in complex scenarios in the fields of computer vision, voice, natural language processing, data mining, and the like. Particularly, the deep learning technology is largely applied to the cloud intelligent field, and one remarkable characteristic of the cloud intelligent application is that the input data volume is large, and the high requirements on the storage capacity and the computing capacity of the platform are provided) comprising:
a first memory component configured as a first-level (L1) memory cache equivalent to store first data that is transient ([0054], Returning to FIG. 3, the computing device 201 also includes a memory 312. Specifically, the SRAM 308, NRAM431 and WRAM 432 may be regarded as a first level Cache (L1 Cache) of the computing device 201, where the first level Cache is a first level Cache of the computing device 201, and although the input/output speed of the first level Cache is fast, the capacity of the first level Cache may not be too large due to the limited area of the processor core 306);
a second memory component configured as a second-level (L2) memory cache equivalent to store second data that is not held within the in-memory data store ([0054], …The memory 312 is a second level Cache (L2 Cache) of the computing device 201, which is a second level Cache of the computing device 201, and may be disposed inside or outside a chip, where the internal chip second level Cache operates at the same speed as the main frequency, and the external second level Cache typically only has half of the main frequency. The access speed of the second-level buffer is lower than that of the first-level buffer, but the space of the second-level buffer is larger than that of the first-level buffer); a third memory component configured as a third-level (L3) memory cache equivalent to store third data ([0054], …DRAM 204 is a tertiary Cache (L3 Cache), which has a lower access speed than the secondary Cache, but has a much larger space than the secondary Cache).
Cambrian does not expressly teach store data to each cache level according to access frequency thresholds. In an analogous art of cache management in an artificial intelligence (AI) computing environment, Maharana teaches multiple levels of cache memory, storing data to higher performance memory tier when data access frequency is higher than a threshold, storing data to lower performance memory tier when data access frequency is lower than a threshold ([0034], the data orchestrator 113 can optionally separate data access requests into different streams and determine current data placement in the memory subsystem 111 based on characteristics of the data streams. For example, data accessed randomly with a frequency higher than a threshold can be placed in a media (e.g., 109A) of a high-performance tier, data accessed randomly with a frequency lower than the threshold hold can be placed in a media of a medium-performance tier, and data accessed sequentially can be placed in a media (e.g., 109N) of a low-performance tier. For example, the media (e.g., 109A) of the high-performance tier can be implemented using DRAM {L1 cache} and/or cross point memory; the media of the medium-performance tier can be implemented using flash memory with single level cells (SLCs) {L2 cache}; and the media (e.g., 109N) of the low-performance tier can be implemented using flash memory with triple level cells (TLCs) {L3 cache} and/or quad-level cells (QLCs) {L4 cache}. As the data usage frequency changes, the data orchestrator 113 can change the data placement in different memory tiers; [0134], The cache controller 273 monitors a higher performance memory used as a cache relative to a lower performance memory, analyzes the usage of the cache, optimizes the usage of the cache, and manages the use of the cache).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention was made, with the teachings of Cambrian and Maharana before them, to combine Cambrian’s multiple levels of cache with Maharana’s placing more frequently accessed data in higher speed memory and using each data access frequency thresholds to determine data placement in a higher speed cache or lower speed cache to optimize the performance of the memory system because more frequently accessed data can be served by a faster memory tier. Thus, the combination teaches
Using L2 frequency threshold to determine whether data is stored in L2 cache or L3 cache:
store in L2 cache when access frequency greater than L2 frequency threshold
store in L3 cache when access frequency less than L2 frequency threshold; likewise,
Using L3 frequency threshold to determine whether data is stored in L3 cache or L4 cache:
store in L3 cache when access frequency greater than L3 frequency threshold
store in L4 cache when access frequency less than L3 frequency threshold
Thus, the combination of Cambrian and Maharana teaches a second memory component configured as a second-level (L2) memory cache equivalent to store second data that is not held within the in-memory data store and is accessed at greater than an L2 frequency threshold; a third memory component configured as a third-level (L3) memory cache equivalent to store third data that is accessed at less than the L2 frequency threshold and at greater than an L3 frequency threshold; and a fourth memory component configured as a fourth-level (L4) memory cache equivalent to store fourth data that is accessed at less than the L3 frequency threshold.
Regarding claim(s) 7, the combination of Cambrian and Maharana further teaches wherein the AI computing environment comprises one or more AI models assigned to operate across one or more levels of the L1 memory cache equivalent, the L2 memory cache equivalent, the L3 memory cache equivalent, the L4 memory cache equivalent, or a combination thereof (
Cambrian, [0054], Returning to FIG. 3, the computing device 201 also includes a memory 312. Specifically, the SRAM 308, NRAM431 and WRAM 432 may be regarded as a first level Cache (L1 Cache) of the computing device 201, where the first level Cache is a first level Cache of the computing device 201, and although the input/output speed of the first level Cache is fast, the capacity of the first level Cache may not be too large due to the limited area of the processor core 306;
Maharana, [0040], When a data item being accessed is in the slower set of memory but not in the faster set of memory, the data item can be accessed in the slower set of memory directly, or swapped to the faster set of memory for accessing in the faster set of memory, or cached in the faster set of memory; [0034], the data orchestrator 113 can optionally separate data access requests into different streams and determine current data placement in the memory subsystem 111 based on characteristics of the data streams. For example, data accessed randomly with a frequency higher than a threshold can be placed in a media (e.g., 109A) of a high-performance tier, data accessed randomly with a frequency lower than the threshold hold can be placed in a media of a medium-performance tier, and data accessed sequentially can be placed in a media (e.g., 109N) of a low-performance tier. …. As the data usage frequency changes, the data orchestrator 113 can change the data placement in different memory tiers; [0134], The cache controller 273 monitors a higher performance memory used as a cache relative to a lower performance memory, analyzes the usage of the cache, optimizes the usage of the cache, and manages the use of the cache).
Regarding claim(s) 8, the combination of Cambrian and Maharana further teaches wherein the AI computing environment comprises a plurality of processors respectively executing the one or more AI models as sub-tasks (Cambrian, [0038], The computing device 201 is configured to process input data such as computer vision, voice, natural language, and data mining, where the computing device 201 is configured as a multi-core hierarchical structure, and the computing device 201 is a system-on-chip (soc) including a plurality of computing clusters (clusters), each of which includes a plurality of processor cores; Fig. 9 & [0062], In step 901, data is split into sub-data, referred to herein as a right stripe matrix, based on the number of processor cores).
Regarding claim(s) 9, the combination of Cambrian and Maharana further teaches wherein the L1 memory cache equivalent, the L2 memory cache equivalent, the L3 memory cache equivalent, the L4 memory cache equivalent, or a combination thereof store contextual data for augmenting one or more inputs to the one or more AI models (Maharana [0021], tagging data access requests to indicate the contexts of the respective data, in addition to the identification of the address of the data involved in the requests. The memory sub-system manages the data placement in physical memory regions such that data of different contexts is separated into different physical memory regions).
Allowable Subject Matter
4. Claims 2-6, 10-14, 16-17, 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/TRACY C CHAN/ Primary Examiner, Art Unit 2138