DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Interpretation Under - 35 USC § 112(f)
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
Use of the word “means” (or “step for”) in a claim with functional language creates a rebuttable presumption that the claim element is to be treated in accordance with 35 U.S.C. 112(f) (pre-AIA 35 U.S.C. 112, sixth paragraph). The presumption that 35 U.S.C. 112(f) (pre-AIA 35 U.S.C. 112, sixth paragraph) is invoked is rebutted when the function is recited with sufficient structure, material, or acts within the claim itself to entirely perform the recited function.
Absence of the word “means” (or “step for”) in a claim creates a rebuttable presumption that the claim element is not to be treated in accordance with 35 U.S.C. 112(f) (pre-AIA 35 U.S.C. 112, sixth paragraph). The presumption that 35 U.S.C. 112(f) (pre-AIA 35 U.S.C. 112, sixth paragraph) is not invoked is rebutted when the claim element recites function but fails to recite sufficiently definite structure, material or acts to perform that function.
Claim elements in this application that use the word “means” (or “step for”) are presumed to invoke 35 U.S.C. 112(f) except as otherwise indicated in an Office action. Similarly, claim elements that do not use the word “means” (or “step for”) are presumed not to invoke 35 U.S.C. 112(f) except as otherwise indicated in an Office action.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
graphics rendering logic in claims 1-17, and 20
indication logic in claims 6-8
geometry processing logic in claims 1-17
tiling unit in claim 8
image rendering logic in claim 8
post-processing logic in claim 14
video encoding logic in claim 15
motion estimation logic in claim 16
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Against Patent # 11,348,197
Claims 1-12, 18, 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 1, 2, 4, 5, 7, 8, 13, 14, 14, 14, 11, 19, 20 respectively (consecutively in order) of U.S. Patent No. 11,348,197.
Instant Application
US Patent 11,348,197
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Although the claims at issue are not identical, they are not patentably distinct from each other because, the claims of the instant application are obvious variant of the corresponding ones of the US Patent No. 11,348,197. Furthermore, the scopes of the claims on the instant application are also met and encompassed by the corresponding ones of the Patent No. 11,348,197.
The apparent difference between the conflicting claims mainly arise from the style of limitation recitation and relative placement of conflicting elements within the claims’ body.
Limitation ‘complexity of the region’ in claims are understood as an obvious variant of ‘cost indication’ in the Patent.
Against Patent # 10,902,550
Claims 1-12, 18, 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 1, 2, 2, 3, 5, 6, 11, 13, 13, 14, 9, 19, 20 respectively (consecutively in order) of U.S. Patent No. 10,902,550.
Instant Application
US Patent 10,902,550.
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Although the claims at issue are not identical, they are not patentably distinct from each other because, the claims of the instant application are obvious variant of the corresponding ones of the US Patent No. 10,902,550. Furthermore, the scopes of the claims on the instant application are also met and encompassed by the corresponding ones of the Patent No. 10,902,550.
The apparent difference between the conflicting claims mainly arise from the style of limitation recitation and relative placement of conflicting elements within the claims’ body.
Limitation ‘complexity of the region’ in claims is understood as an obvious variant of ‘cost indication’ in the Patent.
Against Patent # 10,395,336
Claims 1-6, 9-12, 18, 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 1, 1, 2, 2, 2, 6, 2, 6, 8, 19, 20 respectively (consecutively in order) of U.S. Patent No. 10,395,336.
Instant Application
US Patent 10,395,336.
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Although the claims at issue are not identical, they are not patentably distinct from each other because, the claims of the instant application are obvious variant of the corresponding ones of the US Patent No. 11,348,197. Furthermore, the scopes of the claims on the instant application are also met and encompassed by the corresponding ones of the Patent No. 11,348,197.
The apparent difference between the conflicting claims mainly arise from the style of limitation recitation and relative placement of conflicting elements within the claims’ body.
Limitation ‘complexity of the region’ in claims is understood as an obvious variant of ‘cost indication’ in the Patent.
Against Patent # 12,100,062
Claims 1-13, 18, 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 1, 7, 3, 7, 8, 9, 13, 2, 12, 3, 4, 11, 19-20 respectively (consecutively in order) of U.S. Patent No. 12,100,062.
Instant Application
US Patent 12,100,062
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Although the claims at issue are not identical, they are not patentably distinct from each other because, the claims of the instant application are obvious variant of the corresponding ones of the US Patent No. 11,348,197. Furthermore, the scopes of the claims on the instant application are also met and encompassed by the corresponding ones of the Patent No. 11,348,197.
The apparent difference between the conflicting claims mainly arise from the style of limitation recitation and relative placement of conflicting elements within the claims’ body.
Limitation ‘complexity of the region’ in claims is understood as an obvious variant of ‘cost indication’ in the Patent.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-9, 11-13, 18 is/are rejected under 35 U.S.C. 102(a)(1) and/or 102(a)(2) as being anticipated by Morphet (US 20140333619 A1).
Regarding claim1, Morphet discloses Graphics rendering logic (graphics renderer claim 1, system of fig. 1 except ISP 6+8) configured to: process graphics data to render an image, thereby producing rendered image values (That is, when the system begins to render small parts of the screen (called macro tiles) before the whole image has been stored in the display list memory. The rendering of a macro tile is known as a "partial render" and typically renders only a fraction of the number of objects that will eventually be rendered in that macro tile, ¶0065); and
output the rendered image values and an indication obtained whilst rendering the image (The parameter management system allows the display list memory associated with the macro tile to be released and used for the storage of further objects. This allows scenes of arbitrary complexity to be rendered in a finite amount of memory space, ¶0065.
The tile accelerator works by calculating the set of tiles in which each object must be rendered, and adding the object to each of those tiles by writing an object pointer into the appropriate list. In a basic system a single copy of the parameter data is written to the display list memory, but in a system using parameter management a copy of the data must be written for each macro tile in which the object is to be rendered. This arrangement is shown in the lower part of FIG. 2, ¶0067).
Regarding claim 2, Morphet discloses graphics rendering logic of claim 1, wherein the rendered image values are for a region of the image, the indication having been obtained whilst rendering the region of the image (An apparatus and a method for generating 3-dimensional computer graphic images. The image is first sub-divided into a plurality of rectangular areas. A display list memory is loaded with object data for each rectangular area. The image and shading data for each picture element of each rectangular area are derived from the object data in the image synthesis processor and a texturizing and shading processor, Abstract
Culling in the Tile Accelerator operates when parameter management is active. That is, when the system begins to render small parts of the screen (called macro tiles) before the whole image has been stored in the display list memory. The rendering of a macro tile is known as a "partial render" and typically renders only a fraction of the number of objects that will eventually be rendered in that macro tile. The parameter management system allows the display list memory associated with the macro tile to be released and used for the storage of further objects. This allows scenes of arbitrary complexity to be rendered in a finite amount of memory space, ¶0065).
Regarding claim 3, Morphet discloses graphics rendering logic of claim 1, further configured to obtain an indication for each of a plurality of regions of the image (An apparatus and a method for generating 3-dimensional computer graphic images. The image is first sub-divided into a plurality of rectangular areas. A display list memory is loaded with object data for each rectangular area. The image and shading data for each picture element of each rectangular area are derived from the object data in the image synthesis processor and a texturizing and shading processor, Abstract
That is, when the system begins to render small parts of the screen (called macro tiles) before the whole image has been stored in the display list memory. The rendering of a macro tile is known as a "partial render" and typically renders only a fraction of the number of objects that will eventually be rendered in that macro tile, ¶0065
The parameter management system allows the display list memory associated with the macro tile to be released and used for the storage of further objects. This allows scenes of arbitrary complexity to be rendered in a finite amount of memory space, ¶0065.
The tile accelerator works by calculating the set of tiles in which each object must be rendered, and adding the object to each of those tiles by writing an object pointer into the appropriate list. In a basic system a single copy of the parameter data is written to the display list memory, but in a system using parameter management a copy of the data must be written for each macro tile in which the object is to be rendered. This arrangement is shown in the lower part of FIG. 2, ¶0067).
Regarding claim 4, Morphet discloses graphics rendering logic of claim 3, wherein the indication for each region of the plurality of regions is obtained whilst rendering the corresponding region of the image (An apparatus and a method for generating 3-dimensional computer graphic images. The image is first sub-divided into a plurality of rectangular areas. A display list memory is loaded with object data for each rectangular area. The image and shading data for each picture element of each rectangular area are derived from the object data in the image synthesis processor and a texturizing and shading processor, Abstract
That is, when the system begins to render small parts of the screen (called macro tiles) before the whole image has been stored in the display list memory. The rendering of a macro tile is known as a "partial render" and typically renders only a fraction of the number of objects that will eventually be rendered in that macro tile, ¶0065
The parameter management system allows the display list memory associated with the macro tile to be released and used for the storage of further objects. This allows scenes of arbitrary complexity to be rendered in a finite amount of memory space, ¶0065.
The tile accelerator works by calculating the set of tiles in which each object must be rendered, and adding the object to each of those tiles by writing an object pointer into the appropriate list. In a basic system a single copy of the parameter data is written to the display list memory, but in a system using parameter management a copy of the data must be written for each macro tile in which the object is to be rendered. This arrangement is shown in the lower part of FIG. 2, ¶0067).
Regarding claim 5, Morphet discloses graphics rendering logic of claim 3, wherein the graphics data is processed using a rendering space sub-divided into a plurality of tiles, and the regions of the image are sets of one or more tiles of the rendering space (An apparatus and a method for generating 3-dimensional computer graphic images. The image is first sub-divided into a plurality of rectangular areas. A display list memory is loaded with object data for each rectangular area. The image and shading data for each picture element of each rectangular area are derived from the object data in the image synthesis processor and a texturizing and shading processor, Abstract
That is, when the system begins to render small parts of the screen (called macro tiles) before the whole image has been stored in the display list memory. The rendering of a macro tile is known as a "partial render" and typically renders only a fraction of the number of objects that will eventually be rendered in that macro tile, ¶0065
The parameter management system allows the display list memory associated with the macro tile to be released and used for the storage of further objects. This allows scenes of arbitrary complexity to be rendered in a finite amount of memory space, ¶0065.
The tile accelerator works by calculating the set of tiles in which each object must be rendered, and adding the object to each of those tiles by writing an object pointer into the appropriate list. In a basic system a single copy of the parameter data is written to the display list memory, but in a system using parameter management a copy of the data must be written for each macro tile in which the object is to be rendered. This arrangement is shown in the lower part of FIG. 2, ¶0067).
Regarding claim 6, Morphet discloses graphics rendering logic of claim 5, wherein the sets of one or more tiles each comprise a plurality of tiles, and wherein the graphics rendering logic comprises indication logic configured to:
obtain a respective indication for each of the tiles of a set of tiles; and determine the indication for the set of tiles based on the indications of the tiles within that set (An apparatus and a method for generating 3-dimensional computer graphic images. The image is first sub-divided into a plurality of rectangular areas. A display list memory is loaded with object data for each rectangular area. The image and shading data for each picture element of each rectangular area are derived from the object data in the image synthesis processor and a texturizing and shading processor, Abstract
That is, when the system begins to render small parts of the screen (called macro tiles) before the whole image has been stored in the display list memory. The rendering of a macro tile is known as a "partial render" and typically renders only a fraction of the number of objects that will eventually be rendered in that macro tile, ¶0065
The parameter management system allows the display list memory associated with the macro tile to be released and used for the storage of further objects. This allows scenes of arbitrary complexity to be rendered in a finite amount of memory space, ¶0065.
The tile accelerator works by calculating the set of tiles in which each object must be rendered, and adding the object to each of those tiles by writing an object pointer into the appropriate list. In a basic system a single copy of the parameter data is written to the display list memory, but in a system using parameter management a copy of the data must be written for each macro tile in which the object is to be rendered. This arrangement is shown in the lower part of FIG. 2, ¶0067
Z range culling works by reducing the set of tiles to which the objects are added. This is done by comparing the Z range of the object with the stored Z range for the tile, for each tile in which the object occurs. Tiles can then be removed from the set when the test fails. The comparison test must of course be chosen according to the DCM of the object.
The reduction in memory consumption occurs because the reduced set of tiles also tends to use fewer macro tiles, and therefore fewer copies of the object parameter data must be made, ¶0068-0069).
Regarding claim 7, Morphet discloses graphics rendering logic of claim 6, wherein the indication logic is configured to determine the indication for a set of tiles by determining: (i) an average of the cost indications of the tiles within that set, (ii) a sum of the indications of the tiles within that set, (iii) a maximum of the indications of the tiles within that set, or (iv) a number of the tiles within that set which have indications above a threshold (Table 2, ¶0072, ¶0074, fig. 8 meets at least items (iii) & (iv)).
Regarding claim 8, Morphet discloses graphics rendering logic of claim 1, further comprising geometry processing logic (Tile accelerator 2, fig. 1), image rendering logic (display list memory 4, ¶0065), and indication logic (parameter management system, ¶0004, ¶0010-0011, ¶0065, ¶0070), the indication logic being configured to obtain the indication (The parameter management system allows the display list memory associated with the macro tile to be released and used for the storage of further objects, ¶0065.
… wherein the identifying data for the object comprises a pointer to a location in a memory at which parameter data for the object can be obtained…, - claim 2), and
the graphics data being processed using a rendering space, wherein the geometry processing logic includes a tiling unit configured to generate control streams for tiles of the rendering space indicating which primitives are present in the tiles (In FIG. 1, the Tile Accelerator 2 is the part of the system that processes the input data, performs the tiling calculations, and writes object parameter and pointer data to the display list memory 4. The layout of data in the display list memory is as shown in FIG. 2, ¶0004
Culling in the Tile Accelerator operates when parameter management is active. That is, when the system begins to render small parts of the screen (called macro tiles) before the whole image has been stored in the display list memory. The rendering of a macro tile is known as a "partial render" and typically renders only a fraction of the number of objects that will eventually be rendered in that macro tile. The parameter management system allows the display list memory associated with the macro tile to be released and used for the storage of further objects. This allows scenes of arbitrary complexity to be rendered in a finite amount of memory space, ¶0065), wherein the indication logic is implemented as part of the geometry processing logic (this is a definitional arbitrary grouping, which is understood met for units 2, 4 and 5, fig. 1), and
wherein the image rendering logic is configured to render primitives in tiles of the rendering space in accordance with the generated control streams (Abstract, ¶0065-0068).
Regarding claim 9, Morphet discloses graphics rendering logic of claim 1, wherein the indication is suggestive of a complexity of the region of the rendered image (The enhancement therefore makes it possible to render arbitrarily complex scenes with reasonable efficiency while using only a limited amount of display list memory, ¶0006
This allows scenes of arbitrary complexity to be rendered in a finite amount of memory space, ¶0065).
Regarding claim 11, Morphet discloses graphics rendering logic of claim 1, wherein the indication is suggestive of a cost associated with processing the rendered image values (The enhancement therefore makes it possible to render arbitrarily complex scenes with reasonable efficiency while using only a limited amount of display list memory, ¶0006
This allows scenes of arbitrary complexity to be rendered in a finite amount of memory space, ¶0065).
Regarding claim 12, Morphet discloses graphics rendering logic of claim 2, wherein the indication is based on one or more of: (i) a number of primitives in the region; (ii) object types associated with primitives in the region; (iii) region coverage area of primitives in the region; (iv) textures to be applied to primitives in the region during rendering of the region; (v) a user input; and (vi) an indication associated with a corresponding image region in a previous frame, wherein the image represents a frame of a sequence of frames (In a basic system a single copy of the parameter data is written to the display list memory, but in a system using parameter management a copy of the data must be written for each macro tile in which the object is to be rendered, ¶0067
Culling objects in the ISP parameter fetch is slightly simpler than culling in the tile accelerator, since the parameter fetch hardware and ISP are always operating on the same tile at the same time, ¶0074.
The Z range of the object itself is more problematic, since it would defeat the purpose of culling if it were necessary to read the object parameters from memory in order to compute the Z range. Instead, all appropriate information (the Z range and DCM) must be read from the object pointer, by the parameter fetch unit 8, ¶0075).
Regarding claim 13, Morphet discloses graphics rendering logic of claim 1, wherein the indication is based on one or more factors which are used to improve the performance of processing the rendered image values (The enhancement therefore makes it possible to render arbitrarily complex scenes with reasonable efficiency while using only a limited amount of display list memory, ¶0006
This allows scenes of arbitrary complexity to be rendered in a finite amount of memory space, ¶0065).
Regarding method claim(s) 18, although wording is different, the material is considered substantively equivalent to the claim(s) 1 as described above.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 10, 14-16, 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Morphet in view of MAMMOU et al. (US 20150092856 A1, hereinafter MAMMOU).
Regarding claim 10, Morphet discloses graphics rendering logic of claim 9, except, wherein a high indication for a region is suggestive of high detail in the region.
However, MAMMOU discloses a system and method for exploiting camera and depth information associated with rendered video frames, such as those rendered by a server operating as part of a cloud gaming service, to more efficiently encode the rendered video frames for transmission over a network (Abstract). MAMMOU further discloses that camera and depth information analyzer 302 is configured to process virtual camera information 306 and depth information 304 to adapt a rate control algorithm performed by video encoder 106 to encode sequence of rendered video frames 110. The rate control algorithm is performed by video encoder 106 to determine the number of bits to use to quantize a residual, such as residual 112, of an encoded block of pixels prior to transmitting it to a receiving device. Camera and depth information analyzer 302 specifically exploits the depth information 304 and the virtual camera information 306 to adapt the rate control algorithm such that the residual is quantized using a larger number of bits if its image content depicts an object (or objects) closer to the virtual camera and a smaller number of bits if its image content depicts an object (or objects) comparatively farther away from the virtual camera. The closeness of the object (or objects) depicted by the image content of a residual can be determined, for example, based on the average or the median depth value of the pixels in the block of pixels associated with the residual (¶0035).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the invention of Morphet with the teaching of MAMMOU of exploiting camera and depth information associated with rendered video frames to more efficiently encode the rendered video frames, wherein macro tiles of the screen rendering portion using the Z Range culling in the tile accelerator of Morphet uses rate control hint 310 such that the residual is quantized using a larger number of bits if its image content depicts an object closer to the virtual camera (understood as preserving high details in the region) and a smaller number of bits if its image content depicts an object (or objects) comparatively farther away from the virtual camera (see MAMMOU, ¶0035, and Z culling based on depth in ¶0065-0068 in Morphet), to obtain, wherein a high indication for a region is suggestive of high detail in the region, because, combining prior art elements ready to be improved according to known method to yield predictable results is obvious (see MPEP §2143.I). Furthermore, such combination would enhance the efficiency of the overall rendering system by dynamically controlling the bit rates of the encoded rendered frames.
Regarding claim 14, Morphet discloses a computing system (¶0002, fig. 1) comprising: graphics rendering logic as set forth in claim 1 (see substantively similar claim 1 rejection above).
Morphet is not found disclosing expressly the limitation of post-processing logic configured to process the rendered image values in dependence on the indication.
However, MAMMOU discloses a system and method for exploiting camera and depth information associated with rendered video frames, such as those rendered by a server operating as part of a cloud gaming service, to more efficiently encode the rendered video frames for transmission over a network (Abstract). MAMMOU further discloses
camera and depth information analyzer 302 is configured to process depth information 304 and virtual camera information 306 to provide a motion hint 308 to guide the motion-compensation prediction process performed by video encoder 106. In one embodiment, motion hint 308 is a predicted motion field that includes a number of different motion vectors. The motion vectors are associated with different image regions in current video frame 118 and predict the motion of the particular image region they are associated with from reference video frame 114 (¶0033). MAMMOU further discloses that camera and depth information analyzer 302 is configured to process virtual camera information 306 and depth information 304 to adapt a rate control algorithm performed by video encoder 106 to encode sequence of rendered video frames 110. The rate control algorithm is performed by video encoder 106 to determine the number of bits to use to quantize a residual, such as residual 112, of an encoded block of pixels prior to transmitting it to a receiving device. Camera and depth information analyzer 302 specifically exploits the depth information 304 and the virtual camera information 306 to adapt the rate control algorithm such that the residual is quantized using a larger number of bits if its image content depicts an object (or objects) closer to the virtual camera and a smaller number of bits if its image content depicts an object (or objects) comparatively farther away from the virtual camera. The closeness of the object (or objects) depicted by the image content of a residual can be determined, for example, based on the average or the median depth value of the pixels in the block of pixels associated with the residual (¶0035). MAMMOU further discloses that, camera and depth information analyzer 302 can provide motion vector 416 (or some information determined based off of motion vector 416) to video encoder 106 as part of motion hint 308 (¶0043).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the invention of Morphet with the teaching of MAMMOU of exploiting camera and depth information associated with rendered video frames to more efficiently encode the rendered video frames, wherein macro tiles of the screen rendering portion using the Z Range culling in the tile accelerator of Morphet uses rate control hint 310 such that the residual is quantized using a larger number of bits if its image content depicts an object closer to the virtual camera (understood as preserving high details in the region) and a smaller number of bits if its image content depicts an object (or objects) comparatively farther away from the virtual camera (see MAMMOU, ¶0035, and Z culling based on depth in ¶0065-0068 in Morphet), to obtain, post-processing logic configured to process the rendered image values in dependence on the indication, because, combining prior art elements ready to be improved according to known method to yield predictable results is obvious (see MPEP §2143.I). Furthermore, such combination would enhance the efficiency of the overall rendering system by dynamically controlling the bit rates of the encoded rendered frames.
Regarding claim 15, Morphet in view of MAMMOU discloses the computing system of claim 14, wherein the post-processing logic comprises video encoding logic configured to encode the rendered image values in dependence on the indication (MAMMOU: Abstract, ¶0033, 0037, ¶0043, claims 1-3).
Regarding claim 16, Morphet in view of MAMMOU discloses the computing system of claim 14, wherein the post-processing logic comprises motion estimation logic configured to apply motion estimation to the rendered image values in dependence on the indication (MAMMOU: Abstract, ¶0033, 0037, ¶0043, claims 1-3).
Regarding method claim(s) 19, although wording is different, the material is considered substantively equivalent to the claim(s) 14 as described above.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Morphet in view of Murrin et al. (US 20160359579 A1, hereinafter Murrin).
Regarding claim 20, Morphet discloses a non-transitory computer readable storage medium having stored thereon a computer readable description of an integrated circuit that, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture a computing system which comprises graphics rendering logic configured to:
process graphics data to render an image, thereby producing rendered image values;
output the rendered image values and an indication obtained whilst rendering the image (see substantively similar claim 1 rejection above).
Morphet is not found discloses a non-transitory computer readable storage medium having stored thereon a computer readable description of an integrated circuit that, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture the computing system which comprises graphics rendering logic configured to perform the steps described above.
However, Murrin discloses a non-transitory computer readable storage medium having stored thereon a computer readable description of an integrated circuit that, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture the computing system which comprises graphics rendering logic configured to perform certain method steps (claim 16).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to implement the computing system of Morphet using the integrated circuit manufacturing system of Murrin, to obtain, a non-transitory computer readable storage medium having stored thereon a computer readable description of an integrated circuit that, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture the computing system which comprises graphics rendering logic configured to perform the steps described above with respect to Morphet, because. combining prior art elements ready to be improved according to known method to yield predictable results is obvious (see MPEP §2143.I).
Allowable Subject Matter
Claim 17 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 17, prior arts of record taken alone or in combination fails to reasonably disclose or suggest,
wherein the graphics rendering logic is configured to obtain an indication for each of a plurality of regions of the image whilst rendering the respective region, and wherein the computing system is configured to cause the post-processing logic to process regions of the image in dependence on the respective indications by controlling one or both of: an order in which regions of the image are processed by the post-processing logic, and a level of quality with which regions of the image are processed by the post- processing logic.
Conclusion
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/NURUN FLORA/Primary Examiner, Art Unit 2619
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