DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on:
August 09, 2024;
May 14, 2025;
October 31, 2025;
are being considered by the examiner.
Drawings
The drawings were received on August 08, 2024. These drawings are acceptable.
Claim Objections
Claims 1 and 17 are objected to because of the following informalities:
Claim 1, line 5: the phrase “a pattern barrier on the the surface” contains a typographical error in a redundant “the.”
Claim 17: the claim recites: “wherein the pattern barrier is a selected on of: epoxy or resin.” which appears to contain two different typographical errors. First, the use of “on of” instead of “one of.” The second is the phrase “pattern barrier” being selected from one of epoxy or resin. This does not appear to be discussed in the specification, and differs from previous claims 2 and 3 which define the adhesive as being epoxy or resin. This is consistent with the specification. It appears that claim 17 intends to require “wherein the adhesive is a selected one of : epoxy or resin” instead of stating the pattern barrier is epoxy or resin. The examiner interprets the claim in this fashion, since stating the pattern barrier is epoxy or resin does not appear to make sense contextually.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park et al. (U.S. Patent Application Publication 2011/0042797, hereinafter referred to as “PARK”). PARK anticipates claims: (a)
1 and 14. A package (400 and method of identifying and applying the structures) comprising:
a substrate (100);
a die (semiconductor chip 150 is interpreted as the die) with a first side (see figure 2B, the top side of 150 is interpreted as the first side) and a second side (see figure 2B, the bottom side of 150 is interpreted as the second side) opposite the first side, the second side physically coupled with a surface of the substrate; and
a pattern barrier (first surface portion 110a and second surface portion 110b are interpreted as the pattern barrier, see figures 2A-2E) on the surface of the substrate to reduce a flow of an adhesive on the substrate (see paragraph 0084), wherein the pattern barrier is at least partially within a die shadow area of the die (see figure 2B; the “die shadow area” is interpreted as any portion of the device below the die 150, see figure 2B, which in this case encompasses all structures except 150 itself).
2. The package of claim 1, wherein the adhesive is an epoxy (see paragraph 0084).
3. The package of claim 1, wherein the adhesive is a resin (see paragraph 0084).
4. The package of claim 1, wherein the pattern barrier is to reduce the flow of the adhesive when in contact with the pattern barrier (see paragraph 0084).
5. The package of claim 1, wherein the pattern barrier surrounds an area on the surface of the substrate (see figure 1).
6. The package of claim 1, wherein the pattern barrier further includes a chemical barrier (see figure 0084, as the barrier blocks epoxy, a chemical, the barrier is further interpreted as a chemical barrier).
7. The package of claim 6, wherein the chemical barrier includes a material with a high thixotropic index (see paragraph 0092, as layer 110 is a spin-coated material, it is interpreted as having a high thixotropic index).
8. The package of claim 6, wherein the chemical barrier is disposed next to a die edge (see figures 1-2).
9. The package of claim 6, wherein a width of the chemical barrier is less than 150 micrometers (see paragraph 0096).
10. The package of claim 1, wherein the pattern barrier includes a plurality of holes (see figure 2C).
11. The package claim 10, wherein the plurality of holes are arranged in a hexagonal pattern (see figures 1-2, the pattern can be interpreted as forming a portion of a hexagon, and is therefore arranged in a hexagonal pattern).
12. The package claim 10, wherein the plurality of holes are arranged in a square pattern (see figures 1-2, they’re interpreted as being arranged in a square pattern).
13. The package of claim 1, wherein the pattern barrier is formed with laser ablation (this product-by-process limitation does not further structurally define the structure).
15. The method of claim 14, further comprising physically coupling the surface of the substrate with the second side of the die (see figures 1-2).
16. The method of claim 15, further comprising flowing the adhesive between the second side of the die and the surface of the substrate (see figures 1-2).
17. The method of claim 14, wherein the pattern barrier is a selected on of: epoxy or resin (see figures 0084).
18. A package (400 and method of identifying and applying the structures) comprising:
a substrate (100);
a first die (semiconductor chip 150 is interpreted as the first die) with a first side (see figure 2B, the top side of 150 is interpreted as the first side) and a second side (see figure 2B, the bottom side of 150 is interpreted as the second side) opposite the first side, the second side physically coupled with a surface of the substrate;
a pattern barrier (first surface portion 110a and second surface portion 110b are interpreted as the pattern barrier, see figures 2A-2E) on the surface of the substrate to reduce a flow of an adhesive on the substrate (see paragraph 0084), wherein the pattern barrier is at least partially within a die shadow area of the die (see figure 2B; the “die shadow area” is interpreted as any portion of the device below the die 150, see figure 2B, which in this case encompasses all structures except 150 itself);
a second die (the second semiconductor chips 306 and the second substrate 304 are together interpreted as the second die) with a first side (top side) and a second side (bottom side) opposite the first side, the second side of the second die physically coupled with the first side of the first die (see figure 19); and
wherein a fillet formed subsequent to a flow of the adhesive adjacent at an edge surface of the first die perpendicular to the first side of the first die is not in physical contact with the second die coupled with the first die (see figure 19).
19. The package of 18, where in the first side of the first die is etched after the flow of the adhesive and prior to physical coupling of the second side of the second die to the first die (see figure 19; this product-by-process limitation does not further structurally define the claim).
20. The package of claim 18, wherein the second die is a fiber attached unit (FAU) die (see figure 19, the second die is interpreted as a fiber attached unit).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN M BEDTELYON whose telephone number is (571)270-1290. The examiner can normally be reached 8:00am - 4:30pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Uyen-Chau Le can be reached at 571-272-2397. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/John Bedtelyon/Primary Examiner, Art Unit 2874
Prosecution Insights