DETAILED ACTION
This action is responsive to the application filed 8 Aug 24. Claims 1-20 are pending. Claims 1, 13, and 20 are independent.
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Notice of Foreign Priority Claim
Acknowledgment is made of applicant’s claim for foreign priority. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Application Title
The Examiner proposes the below Application Title change in accordance with MPEP 606.01 and MPEP 1302.04(a) to improve the descriptive nature of the title. The Applicant can suggest an alternative title if desired. The Application Title should be changed to the following:
“MEMORY STRUCTURE WITH THREE BIT LINES TO A MEMORY CELL”
Allowable Subject Matter
Claims 3 – 9 and 16 – 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim(s) 11 and 12 is/are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 11 state(s), “wherein each memory transistor comprises a first source/drain and a second source/drain;” This is indefinite because “each … transistor” typically comprises a single source and a single drain. Here a single transistor comprises two sources and two drains.
Claim 11 further state(s), “a plurality of connection pillars configured to connect the first source/drain of the memory transistor to the ground line,” This is indefinite because the language requires either one or both of the sources and/ or drains to be connected to ground. If both the source and drain are connected to “the ground line”, then the short-circuited transistor and not a “participating” part of a memory.
Claim 12 states, “share the same first source/drain;? This is indefinite for the reasons stated above. Additionally, claim 12 depends on rejected claim(s) 11 and is also rejected under 35 U.S.C. 112(b).
Claim Rejections – 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless —
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1, 2, 13, 19, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen, et al, U.S. Patent Application Publication 2022/0415370 (“Chen”).
Regarding claim 1, Chen teaches:
A memory structure comprising: memory transistors arranged in an array along a first direction and a second direction; and (Chen, fig 2, 4A, “[0053] FIG. 2 illustrates a diagram of an exemplary memory device 104, e.g., a NAND Flash memory, having a memory cell array 202 and peripheral circuits including a page buffer 204, a column decoder/bit line driver 206, a row decoder/word line driver 208, a voltage generator 210, control logic 212, registers 214, [0068] FIG. 4A illustrates a perspective view of a portion of an exemplary three-dimensional (3D) memory cell array structure 400, according to some embodiments.”; a 3-dimensional NAND memory array, along a 1st, 2nd, and 3rd direction).
a plurality of bit line groups extending along the first direction and arranged along the second direction, each of which comprises a first bit line, a second bit line, and (Chen, fig 4A, “[0069]The memory cell array structure 400 further includes a plurality of bit lines (BLs) 441 connected with the memory strings 412 over the TSGs 434. [0076] Each memory block 500 can further include a plurality of bit lines (e.g., 52-1 to 52-n) extending in the BL direction and being arranged parallel with each other to distribute along the WL direction”; at least 6 bit lines that extend in the y-direction of fig 4A; that the 6 bit lines are arranged in the x-direction).
a third bit line extending along the first direction and arranged along a third direction; (Chen, fig 3, “[0063] As shown in FIG. 3, each NAND memory string 308 can include… SSGs 310 of NAND memory strings 308 in the same block 304 are coupled through a same source line (SL) 314, e.g., a common SL, for example, to the ground. DSG 312 of each NAND memory string 308 is coupled to a respective bit line 316 from which data can be read via an output bus (not shown), according to some implementations.”; that each of the bit lines at the “top” of the memory array all extend in the z-direction when attaching to a specific memory; thus at least four bit lines extend in the y & z-direction and are arranged in the x-direction).
wherein a memory transistor of the memory transistors is connected to any one of the first bit line, the second bit line, and the third bit line in the same bit line group, or (Chen, fig 3, 4A, “[0065] Peripheral circuits 302 can be coupled to memory cell array 202 through bit lines 316, word lines 318, source lines 314, SSG lines 315, and DSG lines 313…. As described above, peripheral circuits 302 can include any suitable circuits for facilitating the operations of memory cell array 202 by applying and sensing voltage signals and/or current signals through bit lines 316 to and from each target memory cell 306 through word lines 318, source lines 314, SSG lines 315, and DSG lines 313. [0063] In some implementations, SSGs 310 of NAND memory strings 308 in the same block 304 are coupled through a same source line (SL) 314, e.g., a common SL, for example, to the ground.”; that each memory cell is connected to at least one bit line and one word line, that the bit lines can be organized into a grouping based on a block with a common source line 314).
the memory transistor is not connected to the first bit line, the second bit line, and the third bit line in the same bit line group; (Chen, fig 4A, “[0069]The memory cell array structure 400 further includes a plurality of bit lines (BLs) 441 connected with the memory strings 412 over the TSGs 434. [0076] Each memory block 500 can further include a plurality of bit lines (e.g., 52-1 to 52-n) extending in the BL direction and being arranged parallel with each other to distribute along the WL direction”; at least 6 bit lines that extend in the y-direction of fig 4A; that memory cells attached to the 1st, 2nd, 3rd bit lines can be connected to a 4th bit line in the same block 304).
the first direction intersects with the second direction; and both of the first direction and the second direction are perpendicular to the third direction. (Chen, fig 2, 4A, “[0053] FIG. 2 illustrates a diagram of an exemplary memory device 104, e.g., a NAND Flash memory, having a memory cell array 202 and peripheral circuits including a page buffer 204, a column decoder/bit line driver 206, a row decoder/word line driver 208, a voltage generator 210, control logic 212, registers 214, [0068] FIG. 4A illustrates a perspective view of a portion of an exemplary three-dimensional (3D) memory cell array structure 400, according to some embodiments.”; a 3-dimensional NAND memory array, along a 1st, 2nd, and 3rd direction; that each of the 1st, 2nd and 3rd directions are orthogonal to each other).
Regarding claim 2, Chen teaches:
The memory structure according to claim 1, wherein the memory structure further comprises: a plurality of connection pads, (Chen, fig 4A, “[0069] The memory cell array structure 400 further includes a plurality of bit lines (BLs) 441 connected with the memory strings 412 over the TSGs 434.”; that multiple structures “above” the memory cells have a linear composition or conductor which attaches via the bit line to each memory string).
wherein the memory transistor is connected to any one of the first bit line, the second bit line and the third bit line in the same bit line group through the connection pad. (Chen, fig 3, “[0065] Peripheral circuits 302 can be coupled to memory cell array 202 through bit lines 316, word lines 318, source lines 314, SSG lines 315, and DSG lines 313.”; that the multiple structures are “coupled’ to the memory cell via at least their connection “pads” to the BLs 441 to the vertical vit lines 316).
Regarding claim 13, Chen teaches:
A memory comprising: a memory structure; and a peripheral circuit coupled to the memory structure, wherein the memory structure comprises: a plurality of memory transistors arranged in an array along a first direction and a second direction; and (Chen, fig 2, 4A, “[0053] FIG. 2 illustrates a diagram of an exemplary memory device 104, e.g., a NAND Flash memory, having a memory cell array 202 and peripheral circuits including a page buffer 204, a column decoder/bit line driver 206, a row decoder/word line driver 208, a voltage generator 210, control logic 212, registers 214, [0068] FIG. 4A illustrates a perspective view of a portion of an exemplary three-dimensional (3D) memory cell array structure 400, according to some embodiments.”; a 3-dimensional NAND memory array, along a 1st, 2nd, and 3rd direction with peripheral circuits).
a plurality of bit line groups extending along the first direction and arranged along the second direction, each of which comprises a first bit line, a second bit line, and (Chen, fig 4A, “[0069]The memory cell array structure 400 further includes a plurality of bit lines (BLs) 441 connected with the memory strings 412 over the TSGs 434. [0076] Each memory block 500 can further include a plurality of bit lines (e.g., 52-1 to 52-n) extending in the BL direction and being arranged parallel with each other to distribute along the WL direction”; at least 6 bit lines that extend in the y-direction of fig 4A; that the 6 bit lines are arranged in the x-direction).
a third bit line extending along the first direction and arranged along a third direction; (Chen, fig 3, “[0063] As shown in FIG. 3, each NAND memory string 308 can include… SSGs 310 of NAND memory strings 308 in the same block 304 are coupled through a same source line (SL) 314, e.g., a common SL, for example, to the ground. DSG 312 of each NAND memory string 308 is coupled to a respective bit line 316 from which data can be read via an output bus (not shown), according to some implementations.”; that each of the bit lines at the “top” of the memory array all extend in the z-direction when attaching to a specific memory; thus at least four bit lines extend in the y & z-direction and are arranged in the x-direction).
wherein the memory transistor is connected to any one of the first bit line, the second bit line, and the third bit line in the same bit line group, or (Chen, fig 3, 4A, “[0065] Peripheral circuits 302 can be coupled to memory cell array 202 through bit lines 316, word lines 318, source lines 314, SSG lines 315, and DSG lines 313…. As described above, peripheral circuits 302 can include any suitable circuits for facilitating the operations of memory cell array 202 by applying and sensing voltage signals and/or current signals through bit lines 316 to and from each target memory cell 306 through word lines 318, source lines 314, SSG lines 315, and DSG lines 313. [0063] In some implementations, SSGs 310 of NAND memory strings 308 in the same block 304 are coupled through a same source line (SL) 314, e.g., a common SL, for example, to the ground.”; that each memory cell is connected to at least one bit line and one word line, that the bit lines can be organized into a grouping based on a block with a common source line 314).
the memory transistor is not connected to the first bit line, the second bit line, and the third bit line in the same bit line group; (Chen, fig 4A, “[0069]The memory cell array structure 400 further includes a plurality of bit lines (BLs) 441 connected with the memory strings 412 over the TSGs 434. [0076] Each memory block 500 can further include a plurality of bit lines (e.g., 52-1 to 52-n) extending in the BL direction and being arranged parallel with each other to distribute along the WL direction”; at least 6 bit lines that extend in the y-direction of fig 4A; that memory cells attached to the 1st, 2nd, 3rd bit lines can be connected to a 4th bit line in the same block 304).
the first direction intersects with the second direction; and both of the first direction and the second direction are perpendicular to the third direction. (Chen, fig 2, 4A, “[0053] FIG. 2 illustrates a diagram of an exemplary memory device 104, e.g., a NAND Flash memory, having a memory cell array 202 and peripheral circuits including a page buffer 204, a column decoder/bit line driver 206, a row decoder/word line driver 208, a voltage generator 210, control logic 212, registers 214, [0068] FIG. 4A illustrates a perspective view of a portion of an exemplary three-dimensional (3D) memory cell array structure 400, according to some embodiments.”; a 3-dimensional NAND memory array, along a 1st, 2nd, and 3rd direction; that each of the 1st, 2nd and 3rd directions are orthogonal to each other).
Regarding claim 19, Chen teaches The memory according to claim 13, wherein the memory comprises: a read-only memory. (Chen, fig 1, “[0024] However, it will be understood that the inventive concept is not limited to a NAND flash memory and may be applied to various nonvolatile memory devices such as Electrically Erasable and Programmable Read Only Memory (EEPROM),”; a memory that can be EEPROM, or read only).
Regarding claim 20, Chen teaches:
A memory system comprising: a memory device configured to store data; and a controller coupled to the memory device and configured to control the memory device, and the controller comprises a memory, wherein the memory comprises: a memory structure; and a peripheral circuit coupled to the memory structure, wherein the memory structure comprises: a plurality of memory transistors arranged in an array along a first direction and a second direction; and (Chen, fig 2, 4A, “[0053] FIG. 2 illustrates a diagram of an exemplary memory device 104, e.g., a NAND Flash memory, having a memory cell array 202 and peripheral circuits including a page buffer 204, a column decoder/bit line driver 206, a row decoder/word line driver 208, a voltage generator 210, control logic 212, registers 214, [0068] FIG. 4A illustrates a perspective view of a portion of an exemplary three-dimensional (3D) memory cell array structure 400, according to some embodiments.”; a 3-dimensional NAND memory array, along a 1st, 2nd, and 3rd direction).
a plurality of bit line groups extending along the first direction and arranged along the second direction, each of which comprises a first bit line, a second bit line, and (Chen, fig 4A, “[0069]The memory cell array structure 400 further includes a plurality of bit lines (BLs) 441 connected with the memory strings 412 over the TSGs 434. [0076] Each memory block 500 can further include a plurality of bit lines (e.g., 52-1 to 52-n) extending in the BL direction and being arranged parallel with each other to distribute along the WL direction”; at least 6 bit lines that extend in the y-direction of fig 4A; that the 6 bit lines are arranged in the x-direction).
a third bit line extending along the first direction and arranged along a third direction; (Chen, fig 3, “[0063] As shown in FIG. 3, each NAND memory string 308 can include… SSGs 310 of NAND memory strings 308 in the same block 304 are coupled through a same source line (SL) 314, e.g., a common SL, for example, to the ground. DSG 312 of each NAND memory string 308 is coupled to a respective bit line 316 from which data can be read via an output bus (not shown), according to some implementations.”; that each of the bit lines at the “top” of the memory array all extend in the z-direction when attaching to a specific memory; thus at least four bit lines extend in the y & z-direction and are arranged in the x-direction).
wherein the memory transistor is connected to any one of the first bit line, the second bit line, and the third bit line in the same bit line group, or (Chen, fig 3, 4A, “[0065] Peripheral circuits 302 can be coupled to memory cell array 202 through bit lines 316, word lines 318, source lines 314, SSG lines 315, and DSG lines 313…. As described above, peripheral circuits 302 can include any suitable circuits for facilitating the operations of memory cell array 202 by applying and sensing voltage signals and/or current signals through bit lines 316 to and from each target memory cell 306 through word lines 318, source lines 314, SSG lines 315, and DSG lines 313. [0063] In some implementations, SSGs 310 of NAND memory strings 308 in the same block 304 are coupled through a same source line (SL) 314, e.g., a common SL, for example, to the ground.”; that each memory cell is connected to at least one bit line and one word line, that the bit lines can be organized into a grouping based on a block with a common source line 314).
the memory transistor is not connected to the first bit line, the second bit line, and the third bit line in the same bit line group; (Chen, fig 4A, “[0069]The memory cell array structure 400 further includes a plurality of bit lines (BLs) 441 connected with the memory strings 412 over the TSGs 434. [0076] Each memory block 500 can further include a plurality of bit lines (e.g., 52-1 to 52-n) extending in the BL direction and being arranged parallel with each other to distribute along the WL direction”; at least 6 bit lines that extend in the y-direction of fig 4A; that memory cells attached to the 1st, 2nd, 3rd bit lines can be connected to a 4th bit line in the same block 304).
the first direction intersects with the second direction; and both of the first direction and the second direction are perpendicular to the third direction. (Chen, fig 2, 4A, “[0053] FIG. 2 illustrates a diagram of an exemplary memory device 104, e.g., a NAND Flash memory, having a memory cell array 202 and peripheral circuits including a page buffer 204, a column decoder/bit line driver 206, a row decoder/word line driver 208, a voltage generator 210, control logic 212, registers 214, [0068] FIG. 4A illustrates a perspective view of a portion of an exemplary three-dimensional (3D) memory cell array structure 400, according to some embodiments.”; a 3-dimensional NAND memory array, along a 1st, 2nd, and 3rd direction; that each of the 1st, 2nd and 3rd directions are orthogonal to each other).
Claim Rejections – 35 USC § 103
The following is a quotation of 35 U.S.C. 103, which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 10 – 12 are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Lim, et al U.S. Patent Application Publication 2020/0312379 (“Lim”).
Regarding claim 10, Chen teaches the memory structure according to claim 1.
Chen teaches wherein the memory structure further comprises: a plurality of ground lines (Chen, fig 4B, “[0071] Fig 4B illustrates… 3D memory device 450 can include a plurality of channel structure regions, such as memory planes, memory blocks, memory fingers, etc. as shown in FIG. 4B, 3D memory device 450 can include four or more memory planes 460, each of which can include a plurality of memory blocks 465.”; that Source Selection Lines can be unique to each “block” of a memory).
Chen does not explicitly teach extending along the second direction and arranged along the first direction..
Lim teaches extending along the second direction and arranged along the first direction. (Lim, fig 14, “[0128] FIG. 14 illustrates an example of a portion of the memory cell array 110 of FIG. 1. [0130] The cell strings CS in two rows may be connected in common to a ground selection line GSL1 or GSL2 and may be connected to corresponding string selection lines of first to fourth string selection lines SSL1 to SSL4.”; that ground select lines can be unique within a memory block comprising at least three rows orthogonal (extending along 2nd direction, arranged in 1st direction) to bit lines).
In view of the teachings of Lim it would have been obvious for a person of ordinary skill in the art to apply the teachings of Lim to Chen before the effective filing date of the claimed invention in order to teach NAND cell array construction. The teachings of Lim, in the same or in a similar field of endeavor with Chen, can combine explicit ground lines orthogonal to bit lines and ground (source) lines that are arranged by block. The slightly different methods of connecting ground lines to NAND strings merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 11, Chen, as modified by Lim, teaches the memory structure according to claim 10.
Lim further teaches wherein each memory transistor comprises a first source/drain and a second source/drain; and the memory structure further comprises: a plurality of connection pillars configured to connect the first source/drain of the memory transistor to the ground line, and first source/drain of each of the memory transistors arranged along the second direction are connected to the same ground line. (Lim, fig 14, “[0128] FIG. 14 illustrates an example of a portion of the memory cell array 110 of FIG. 1. [0130] The cell strings CS in two rows may be connected in common to a ground selection line GSL1 or GSL2 and may be connected to corresponding string selection lines of first to fourth string selection lines SSL1 to SSL4.”; that ground select lines can be unique within a memory block comprising at least three rows orthogonal (extending along 2nd direction, arranged in 1st direction) to bit lines; that the cell strings are attached to the same GSL in the same (i.e. second direction) line).
In view of the teachings of Lim it would have been obvious for a person of ordinary skill in the art to apply the teachings of Lim to Chen before the effective filing date of the claimed invention in order to teach NAND cell array construction. The teachings of Lim, in the same or in a similar field of endeavor with Chen, can combine explicit ground lines orthogonal to bit lines and ground (source) lines that are arranged by block. The slightly different methods of connecting ground lines to NAND strings merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 12, Chen, as modified by Lim, teaches the memory structure according to claim 11.
Lim further teaches wherein two of the memory transistors adjacent along the first direction share the same first source/drain; and two of the memory transistors adjacent along the first direction share the same ground line. (Lim, fig 14, “[0128] FIG. 14 illustrates an example of a portion of the memory cell array 110 of FIG. 1. [0130] The cell strings CS in two rows may be connected in common to a ground selection line GSL1 or GSL2 and may be connected to corresponding string selection lines of first to fourth string selection lines SSL1 to SSL4.”; that ground select lines can be unique within a memory block comprising at least three rows orthogonal (extending along 2nd direction, arranged in 1st direction) to bit lines; that the cell strings are attached to the same GSL in the same line; that at least three rows of GSL1 share the same ground line. while the GSL2 - GSLn groupings share a different ground line).
In view of the teachings of Lim it would have been obvious for a person of ordinary skill in the art to apply the teachings of Lim to Chen before the effective filing date of the claimed invention in order to teach NAND cell array construction. The teachings of Lim, in the same or in a similar field of endeavor with Chen, can combine explicit ground lines orthogonal to bit lines and ground (source) lines that are arranged by block. The slightly different methods of connecting ground lines to NAND strings merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Claims 14 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Hanzawa, S., U.S. Patent Application Publication 2012/0155162 (“Hanzawa”).
Regarding claim 14, Chen teaches the memory according to claim 13.
Chen does not explicitly teach wherein the peripheral circuit comprises: a plurality of multiplexers, each of which is connected to one bit line in each of the bit line groups, wherein a number of the multiplexers is the same as a number of the bit lines..
Hanzawa teaches wherein the peripheral circuit comprises: a plurality of multiplexers, each of which is connected to one bit line in each of the bit line groups, wherein a number of the multiplexers is the same as a number of the bit lines. (Hanzawa, fig 13A/B/C, “[0168] For example in the case where this memory cell is MC00 (FIG. 4), the memory region control circuit LMARCTL controls the bit line select circuit MUX according to the initial address generated by the address control circuit ADDCTL, and couples each of the global bit lines GBL00L through GBL0nL to each of the bit lines BL0 in the memory tile MTm0 through MTmn (n=127).”; that bit lines are typically controlled by individual multiplexor circuits which are attached to each bit line in a block to deliver various voltages to independent bit lines to either read or to program the individual memory cells).
In view of the teachings of Hanzawa it would have been obvious for a person of ordinary skill in the art to apply the teachings of Hanzawa to Chen before the effective filing date of the claimed invention in order to teach NAND cell array construction. The teachings of Hanzawa, in the same or in a similar field of endeavor with Chen, can combine bit lines explicitly connected to a MUX with Chen’s bitlines that must be independently controlled to deliver different voltages to memory cells. The slightly different methods of connecting bit lines to NAND strings merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 15, Chen, as modified by Hanzawa, teaches the memory according to claim 14.
Hanzawa further teaches wherein the peripheral circuit further comprises: an address decoder connected to the plurality of multiplexers and configured to determine a selected memory transistor of the plurality of memory transistors. (Hanzawa, fig 4, “[0168] For example in the case where this memory cell is MC00 (FIG. 4), the memory region control circuit LMARCTL controls the bit line select circuit MUX according to the initial address generated by the address control circuit ADDCTL, and couples each of the global bit lines GBL00L through GBL0nL to each of the bit lines BL0 in the memory tile MTm0 through MTmn (n=127).”; that bit lines are typically controlled by individual multiplexor circuits which are attached to each bit line in a block to deliver various voltages to independent bit lines to either read or to program the individual memory cells).
In view of the teachings of Hanzawa it would have been obvious for a person of ordinary skill in the art to apply the teachings of Hanzawa to Chen before the effective filing date of the claimed invention in order to teach NAND cell array construction. The teachings of Hanzawa, in the same or in a similar field of endeavor with Chen, can combine bit lines explicitly connected to a MUX with Chen’s bitlines that must be independently controlled to deliver different voltages to memory cells. The slightly different methods of connecting bit lines to NAND strings merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Conclusion
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/Donald HB Braswell/ Primary Examiner, Art Unit 2825