Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 4, 7 – 11 and 14 – 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Raghunathan et al. (US Pat. No. 6195786), hereinafter referred to as Raghunathan.
As to claim 1, Raghunathan discloses an apparatus comprising a first storage circuit (since variable v3 is stored in register R6 in iteration i+1 the old value of v12 is preserved at the input of SUB1 until v3 is born, thus avoiding the spurious operation marked X, shown in FIG. 3, Col. 9, lines 43 - 52) configured to store a first set of previous select values (stored variable assignments, R5 / R6, Fig. 4) transmitted as a first set of previous select signals (mux input selection state, Fig. 6) to a first multiplexer within a datapath (input multiplexers feeding functional units, Fig. 6) of a computing device (synthesized datapath architecture, Fig. 1); and a first control circuit (control logic governing resource sharing and multiplexer configuration, Fig. 8) configured to receive the first set of previous select signals (multiplexer control dependent on prior variable assignment, Fig. 9) and a first set of input toggle likelihood signals (switching activity indication via variable birth/death times, Fig. 2) and based at least in part on the first set of previous select signals (prior selection state considered, Fig. 9) and the first set of input toggle likelihood signals, determine whether to maintain (holding prior mux selection during idle cycles, Fig. 3) the first set of previous select signals or provide a first set of updated select signals to the first multiplexer (holding or reconfiguring multiplexer inputs to suppress spurious switching, Fig. 3).
As to claim 2, Raghunathan et al. discloses the apparatus of claim 1, wherein the first set of input toggle likelihood signals includes a particular input toggle likelihood signal corresponding to a previously-selected data input of the first multiplexer (input switching activity of selected variable, Fig. 2; Fig. 9), the previously-selected data input is a data input selected by application of the first set of previous select signals (prior multiplexer input selection, Fig. 6), and to determine whether to maintain the previous select signals or provide a first set of updated select signals, the first control circuit is further configured to determine whether a value of the particular input toggle likelihood signal indicates a designation of the previously-selected data input as likely to receive a data value change (birth/death time comparison indicating input change likelihood, Fig. 9).
As to claim 3, Raghunathan et al. discloses the apparatus of claim 2, wherein the first control circuit is further configured to, during a cycle for which the first multiplexer is not used to transmit valid data (idle functional-unit cycle, Fig. 3; Fig. 6), in response to determining that the value of the particular input toggle likelihood signal does not indicate a designation of the previously-selected data input as likely to receive a data value change, provide a signal to the first storage circuit causing the first set of previous select signals to be maintained (holding prior multiplexer selection across idle cycle, Fig. 3; Fig. 9), and in response to determining that the value of the particular input toggle likelihood signal indicates a designation of the previously-selected data input as likely to receive a data value change, provide a signal to the first storage circuit causing the first set of updated select signals to be provided to the first multiplexer (reconfiguring multiplexer input selection, Fig. 9).
As to claim 4, Raghunathan et al. discloses the apparatus of claim 1, wherein the first control circuit is further configured to receive a first set of input select signals corresponding to the first multiplexer (multiplexer select control inputs, Fig. 6; Fig. 9), and determine whether the first set of input select signals is configured for passing of data through the first multiplexer (functional-unit active versus idle determination, Fig. 3).
Claims 7 - 11 recite the corresponding limitation of claims 1 - 4. Therefore, they are rejected accordingly.
Claims 14 - 19 recite the corresponding limitation of claims 1 - 4. Therefore, they are rejected accordingly.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5, 6, 12 - 13 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Raghunathan in view of Erickson et al. (US Pub. No. 20030177223), hereinafter referred to as Erickson.
As to claim 5, Raghunathan et al. discloses the apparatus of claim 4, wherein the first control circuit is further configured to using the first set of input select signals, the first set of previous select signals, and the first set of input toggle likelihood signals, generate a first output toggle likelihood signal (derived switching condition indication, Fig. 9)
Erickson discloses, what Raghunathan lacks, provide the first output toggle likelihood signal to the first storage circuit (storing generated condition indicator, stored status data, step 320, Erickson Fig. 3), and forward the first output toggle likelihood signal to an additional control circuit configured to receive an additional set of previous select signals transmitted to an additional multiplexer within the datapath (forwarding condition signal to downstream control logic, alert / notification signal, step 350, Erickson Fig. 3), wherein the first output toggle likelihood signal is among an additional set of input toggle likelihood signals received by the additional control circuit (reuse of generated condition indicator as control input, comparison result propagated via alert signal, steps 340 to 350, Erickson Fig. 3).
Raghunathan and Erickson are analogous art because they are from the problem-solving area of control-based management of system state to reduce unnecessary activity and improve efficiency in computing systems.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Raghunathan and Erickson before him or her, to modify the datapath control circuitry of Raghunathan to include the generation, storage, and propagation of condition-indicating control signals as taught by Erickson
The suggestion and motivation for doing so would have been to extend switching-suppression decisions across multiple control stages and to coordinate control behavior among different system components, thereby improving efficiency and reducing unnecessary activity.
Therefore, it would have been obvious to combine Erickson with Raghunathan to obtain the invention as specified in the instant claim.
As to claim 6, the modified system Raghunathan discloses the apparatus of claim 1, further comprising a second storage circuit configured to store a second set of previous select values transmitted as a second set of previous select signals for a second multiplexer within the datapath (registers storing selection-dependent values, R5 / R6, Fig. 4; Fig. 6), wherein a data output of the first multiplexer is connected as one of a set of data inputs of the second multiplexer (cascaded datapath multiplexers, Fig. 6), and a second control circuit configured to receive the second set of previous select signals and a second set of input toggle likelihood signals (downstream control entity receiving propagated condition signal, alert / status receiver, step 350, Erickson Fig. 3), wherein the second set of input toggle likelihood signals includes an output toggle likelihood signal generated by the first control circuit (propagated condition indicator from upstream control circuit, comparison result 340 forwarded via alert signal 350, Erickson Fig. 3), and based at least in part on the second set of previous select signals and the second set of input toggle likelihood signals, determine whether to maintain the second set of previous select signals or provide a second set of updated select signals to the second multiplexer (multiplexer selection control to suppress switching, Fig. 3).
Claims 12 - 13 recite the corresponding limitation of claims 5 - 6. Therefore, they are rejected accordingly.
Claim 20 recite the corresponding limitation of claim 6. Therefore, they are rejected accordingly.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Pyeon et al. (US Pat. No. 8169849) Methods and systems are provided that allow the method of access to one or more memory banks to be performed using serial access, or using parallel access.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JUANITO C BORROMEO whose telephone number is (571)270-1720. The examiner can normally be reached on Monday - Friday 9 - 5.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Henry Tsai can be reached on 5712724176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/J.C.B/ Assistant Examiner, Art Unit 2184
/HENRY TSAI/ Supervisory Patent Examiner, Art Unit 2184