Prosecution Insights
Last updated: May 29, 2026
Application No. 18/798,978

SEMICONDUCTOR DEVICE

Non-Final OA §102
Filed
Aug 09, 2024
Priority
Aug 09, 2023 — JP 2023-129829
Examiner
LAUTURE, JOSEPH J
Art Unit
2845
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Renesas Electronics Corporation
OA Round
1 (Non-Final)
95%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
96%
With Interview

Examiner Intelligence

Grants 95% — above average
95%
Career Allowance Rate
725 granted / 764 resolved
+26.9% vs TC avg
Minimal +1% lift
Without
With
+0.9%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 8m
Avg Prosecution
9 currently pending
Career history
772
Total Applications
across all art units

Statute-Specific Performance

§101
8.5%
-31.5% vs TC avg
§103
56.2%
+16.2% vs TC avg
§102
13.9%
-26.1% vs TC avg
§112
12.4%
-27.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 764 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Specification The application has not been checked to the extent necessary to determine the presence of all possible typographical and grammatical errors. Applicant’s cooperation is requested in correcting any errors of which he/she may become aware in the application. The Information Disclosure Statements filed 08/09/2024 has been considered. Claim Objection Claim 12 is objected to because of the following informality: the claim recites on line 3 the limitation” the reference voltage”. There is insufficient antecedent basis for this limitation in the claim. Drawing Objection The drawings are objected to because of the following informality: Figures 23, 24 and 25 should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g). Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1, 2 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Fujimoto (US 2002/0024363). Regarding claim 1, Fujimoto teaches in figure (10) a semiconductor device comprising: a first capacitor element (4); a first switch circuit (7) that applies a first input voltage VIN to one end of the first capacitor element (4) in a sampling mode, and holds the first input voltage in the first capacitor element in a hold mode after the sampling mode; a first inversion signal generating circuit (3) (See paragraph [0034]) that generates a voltage that inverts the first input voltage VIN in the sampling mode, and holds the generated voltage in the hold mode; a second capacitor element (6) to which the voltage generated by the first inversion signal generating circuit is applied at one end; and a negative feedback circuit (See paragraph [0034]) that generates an output signal according to the voltage of a first node that is commonly connected to the other end of the first capacitor element (4) and the other end of the second capacitor element (6) in the hold mode, and applies a first feedback signal corresponding to the output signal to one end of the first capacitor element. Regarding claim 2, Fujimoto teaches in figure (10) a semiconductor device wherein the first inversion signal generating circuit (3) comprises an inversion circuit that generates a voltage that inverts the first input voltage VIN in the sampling mode, and a sample-and-hold circuit made of amplifier (2) and capacitor (6 (See paragraph [0049]) that holds the voltage generated by the inversion circuit in the hold mode. Allowable Subject Matter Claims 3-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH J LAUTURE whose telephone number is (571)272-1805. The examiner can normally be reached 9:30 AM-6:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dameon Levi can be reached at 5712722105. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JOSEPH J LAUTURE/ Primary Examiner, Art Unit 2845
Read full office action

Prosecution Timeline

Aug 09, 2024
Application Filed
Mar 04, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12640747
Low-Voltage Reference Buffer with Wide Output Voltage and Current Range
2y 0m to grant Granted May 26, 2026
Patent 12640752
Multiplying digital-to-analog converter
1y 6m to grant Granted May 26, 2026
Patent 12633936
METHOD FOR DETERMINING AN IQ OFFSET
2y 10m to grant Granted May 19, 2026
Patent 12633939
METHODS, SYSTEMS, AND APPARATUSES FOR CALIBRATING RESISTOR-CAPACITOR (RC) CIRCUITS
2y 2m to grant Granted May 19, 2026
Patent 12634106
SERDES LANE CONTROL BONDING SYSTEMS AND METHODS
2y 1m to grant Granted May 19, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
95%
Grant Probability
96%
With Interview (+0.9%)
1y 8m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 764 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month