Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Election/Restrictions
Applicant's election with traverse of election of Species in the reply filed on January 2 is acknowledged. The argument is found persuasive. The election requirement is withdrawn.
Claim Objections
Claim 13 is objected to because of the following informalities: --second value--, should be --second PPC value--. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3, 6-9, 11-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Spijker et al. (US 2007/0024383 A1 and Spijker hereinafter.).
Regarding claim 1, Spijker discloses [fig. 4] a phase-lock loop, comprising: an oscillator [160] having an input for receiving a control signal and an output for providing an output signal having a frequency based on the control signal [para. 43]; a phase detector [100] having a first input for receiving a reference signal, a second input coupled to the output of the oscillator for receiving a feedback signal, and an output for providing a phase-error signal [output of 100] that is indicative of a phase difference between the reference signal and the feedback signal [para. 46]; and a loop filter [para. 44, components 110, 120, 125, 140 and related circuitry] having a first input coupled to the output of the phase detector [110 accepting output of 100], a second input for receiving a proportional-phase-compensation value [120 accepting P-factor], and an output for providing the control signal to the oscillator [output of 140 into 160], wherein the control signal comprises a proportional component [output of 120] which is a combination of the phase-error signal and the proportional-phase-compensation value [p-factor].
Regarding claim 3, Spijker discloses the claimed invention except for the proportional-phase-compensation value has been determined based on a previous value of the phase-error signal. It would have been obvious to one having ordinary skill in the art at the time the invention was made to have updated phase compensation values in a phase locked loop depend on previous values of a phase difference between a reference phase and a feedback (IE previous values) signal since It was known in the art.
Regarding claim 6, Spijker discloses the claimed invention except for the proportional-phase-compensation value has been determined mathematically, in advance, based on loop characteristics. It would have been obvious to one having ordinary skill in the art at the time the invention was made to have phase compensation values in a phase locked loop be determined mathematically and based on a signal feedback since It was known in the art.
Regarding claim 7, Spijker discloses further wherein: the phase-lock loop begins operating in a first operational phase [para. 54, non zero phase offset], during which the proportional-phase-compensation (PPC) value is set at a first PPC value [non zero], and after a first period of time, the proportional-phase-compensation value is updated to a second PPC value [non zero phase offset] based on the phase-error signal during the first operational phase [para. 54].
Regarding claim 8, Spijker discloses the claimed invention except for the first PPC value is 0. It would have been obvious to one having ordinary skill in the art at the time the invention was made to have a first PPC value being an initial or 0 value, since it has been held that discovering an optimum value of a result effective variable involves only routine Skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Regarding claim 9, Spijker discloses further wherein the first PPC value has been determined mathematically, in advance, based on loop characteristics [fig. 5, steps 515 through 530].
Regarding claim 11, Spijker discloses further wherein the loop filter also includes an integrator [125] which, when enabled [via 114], provides an integral component of the control signal, and wherein the integrator is disabled, such that the integral component is 0 [integrator disabled], until satisfaction of a specified criterion [zero phase offset required] following completion of the first period of time, at which point the integrator is enabled [para. 69].
Regarding claim 12, Spijker discloses further wherein the specified criterion comprises the end of a predetermined additional second period of time [fig. 5, step 525 and 535].
Regarding claim 13, Spijker discloses further wherein the specified criterion comprises a condition on the phase-error signal after the proportional-phase-compensation value has been updated to the second value [fig. 5, system switching between a required zero phase offset and a non-zero phase offset].
Regarding claim 14, Spijker discloses further wherein the specified criterion comprises at least one of: (a) a magnitude of at least one value of the phase-error signal falling within a specified range [fig. 5, step 530]; or (b) variation in the phase-error signal falling below a specified threshold [fig. 5, step 530].
Regarding claim 15, Spijker discloses further wherein when the integrator is enabled, the integrator accumulates uncompensated values of the phase-error signal [125 accepting i-factor signal through 180].
Regarding claim 16, Spijker discloses further wherein when the integrator is enabled, the integrator accumulates modified phase-error signal values that are a combination of the phase-error signal and an integral-phase-compensation (IPC) value [output of 125 based on i-factor signal through 180 and input of 180 based on output of 100].
Regarding claim 17, Spijker discloses further wherein the integral-phase-compensation value [output of 125] is determined based on the phase-error signal [input of 125 based on output of 100] during the first operational phase [para. 54, 125 disabled and outputting a frozen signal].
Regarding claim 18, Spijker discloses further wherein: (a) a characteristic phase value [output of 100] is determined based on the phase-error signal during the first operational phase [non zero phase offset (step 520)]; (b) the integral-phase-compensation value is set at a multiple of 2π in a phase-domain representation [output of 125 an oscillation between 0 and 2pi]; and (c) the second PPC value is set as a difference between the characteristic phase value and the integral-phase-compensation value [phase offset a non-zero value and based on phase offset of output of 100].
Regarding claim 19, Spijker discloses further wherein the integral-phase-compensation value is set to the multiple of 2π [an oscillation] in the phase-domain representation nearest to the characteristic phase value [para. 54].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Spijker in view of August et al. (US 20110148489 A1 and August hereinafter.).
Regarding claim 2, Spijker discloses all the features regarding claim 1 as indicated above. Spijker does not explicitly disclose the proportional component is produced by adding the phase-error signal and the proportional-phase-compensation value to provide a result and then applying a gain to the result.
However, August discloses further wherein the proportional component [output of 226] is produced by adding the phase-error signal [FROM PFD] and the proportional-phase-compensation value [from 227] to provide a result and then applying a gain to the result [via 228]. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by Spijker to include the proportional component is produced by adding the phase-error signal and the proportional-phase-compensation value to provide a result and then applying a gain to the result as taught by August to improve phase error and jitter in a phase locked loop.
Claims 4-5 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Spijker in view of Liu et al. (CN 116131846 and Liu hereinafter.).
Regarding claim 4, Spijker discloses all the features regarding claim 1 as indicated above. Spijker does not explicitly disclose wherein the phase-compensation value has been determined based on an average of previous values of the phase-error signal.
However, Liu discloses wherein the phase-compensation value has been determined based on an average of previous values of the phase-error signal [pg. 3]. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by Spijker to include phase-compensation value has been determined based on an average of previous values of the phase-error signal as taught by Liu to improve locking performance in a phase locked loop.
Regarding claim 5, Spijker discloses further wherein the proportional-phase-compensation value has been determined by low-pass filtering the phase-error signal during a prior operational period of the phase-lock loop [Liu, averaging filtering].
Regarding claim 10, Spijker discloses all the features regarding claim 7 as indicated above. Spijker does not explicitly disclose wherein the second PPC value is determined by at least one of: (a) averaging values of the phase-error signal during at least a portion of the first operational phase, or (b) low-pass filtering the phase-error signal during at least a portion of the first operational phase.
However, Liu discloses wherein the second PPC value is determined by at least one of: (a) averaging values of the phase-error signal during at least a portion of the first operational phase [pg. 3], or (b) low-pass filtering the phase-error signal during at least a portion of the first operational phase [pg. 3]. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by Spijker to include the second PPC value is determined by at least one of: (a) averaging values of the phase-error signal during at least a portion of the first operational phase, or (b) low-pass filtering the phase-error signal during at least a portion of the first operational phase as taught by Liu to improve locking performance in a phase locked loop.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over August in view of Spijker.
Regarding claim 20, August discloses a tangible medium storing computer-readable, computer-executable process steps for controlling a phase-lock loop [para. 32] that includes an adder [fig. 2, adder 226] having a first input coupled to a phase-error signal output by phase-detector [from PFD], a second input [from 227], and an output that provides a proportional-phase-compensation value [para. 22]. August does not explicitly disclose wherein said process steps include steps to: begin operating the phase-lock loop in a first operational phase, during which a first value is provided to the second input of the adder; and after a first period of time, instead providing a second value to the second input of the adder. wherein the second value is based on the phase-error signal during the first operational phase.
However, Spijker discloses wherein said process steps include steps to: begin operating the phase-lock loop in a first operational phase [para. 54, non zero phase offset], during which a first value is provided to the second input of the adder [output of 125 when 125 is disabled]; and after a first period of time, instead providing a second value to the second input of the adder [output of 125 when 125 is enabled]. wherein the second value is based on the phase-error signal during the first operational phase [feedback from output of 160 back into 100 based on previous values during transition from desired non zero phase offset to a desired zero phase offset]. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by August to include said process steps include steps to: begin operating the phase-lock loop in a first operational phase, during which a first value is provided to the second input of the adder; and after a first period of time, instead providing a second value to the second input of the adder. wherein the second value is based on the phase-error signal during the first operational phase as taught by Spijker to improve locking times in a phase locked loop.
Conclusion
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/JAMES G YEAMAN/Examiner, Art Unit 2842
/Jessica Han/Supervisory Patent Examiner, Art Unit 2896