DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-14 and 16-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hwang (US PG-Pub No.: 2023/0037646 A1, hereinafter, “Hwang”).
Regarding claim 1, Hwang discloses an integrated circuit device (see Hwang, FIGs. 2A-2C and 11) comprising:
a substrate (201, FIG. 2A) having a cell array area (CA, FIG. 11) and a peripheral circuit area (PA, FIG. 11) including a core area (13P, FIG. 11), the peripheral circuit area (PA) adjacent to the cell array area (CA);
a plurality of cell conductive patterns (216, FIG. 2A) in the cell array area (CA) on the substrate (201), the plurality of cell conductive patterns (216) at a reference vertical level (FIGs. 11 and 2A);
a plurality of lower wiring patterns (238, FIG. 2C) in the peripheral circuit area (PA), the plurality of lower wiring patterns (238) at the reference vertical level (FIGs. 2C and 11);
a capacitor structure (230, ¶ [0018]) in the cell array area (CA), the capacitor structure (230) including a plurality of lower electrodes (220, ¶ [0029]) connected to the plurality of cell conductive patterns (216), respectively (FIG. 2A);
a middle wiring pattern (l241, FIG. 2C) in the peripheral circuit area (PA), the middle wiring pattern (241) at a first vertical level that is farther from the substrate (201) than the reference vertical level and closer to the substrate (201) than a vertical level of an uppermost surface of the substrate (201) of the capacitor structure (230, FIGs. 2A-2C and 11);
a cell protective insulating liner (218, FIG. 2A) in the cell array area (CA), the cell protective insulating liner (218) covering a top surface of each of the plurality of cell conductive patterns (216); and
a peripheral protective insulating liner (217P+239, FIG. 2C) in the peripheral circuit area (PA), the peripheral protective insulating liner (217P+239) covering a surface of the middle wiring pattern (241, FIG. 2C), wherein
at least a portion of the peripheral protective insulating liner (217P+239) has a thickness greater than a thickness of the cell protective insulating liner (218, FIGs. 2A and 2C).
Regarding claim 2, Hwang discloses the integrated circuit device of claim 1, wherein the cell protective insulating liner (218) has a single layer structure comprising a single insulating liner (218), and the peripheral protective insulating liner (217P+239) has a multilayered structure comprising a plurality of insulating liners (217P+239, FIGs. 2A-2C).
Regarding claim 3, Hwang discloses the integrated circuit device of claim 1, wherein the middle wiring pattern (241) is connected to a selected one of the plurality of lower wiring patterns (238, FIG. 2C).
Regarding claim 4, Hwang discloses the integrated circuit device of claim 1, wherein the peripheral protective insulating liner (217P+239) comprises: a first insulating liner (217P) contacting a top surface and sidewalls of the middle wiring pattern (lower 241); and a second insulating liner (239) covering the top surface and the sidewalls of the middle wiring pattern (lower 241), the second insulating liner (239) being apart from the middle wiring pattern (lower 241) with the first insulating liner (217P) between the second insulating liner (239) and the middle wiring pattern (lower 241, FIG. 2C).
Regarding claim 5, Hwang discloses the integrated circuit device of claim 1, wherein the peripheral protective insulating liner (217P+239) comprises: a first insulating liner (217P) contacting a top surface of the middle wiring pattern (241); and a second insulating liner (239) covering the top surface and sidewalls of the middle wiring pattern (241), the second insulating liner (239) being apart from the top surface of the middle wiring pattern (241) with the first insulating liner (217P) between the second insulating liner (239) and the top surface of the middle wiring pattern (241), and the second insulating liner (239) contacting the sidewalls of the middle wiring pattern (241).
Regarding claim 6, Hwang discloses the integrated circuit device of claim 1, further comprising: an isolated insulating pattern (217, ¶ [0027]) in the cell array area (CA), the isolated insulating pattern (217) filling a space between two adjacent ones of the plurality of cell conductive patterns (216), wherein the cell protective insulating liner (218) comprises portions contacting the plurality of lower electrodes (220) and a portion between a top surface of the isolated insulating pattern (217) and the capacitor structure (230, FIG. 2A).
Regarding claim 7, Hwang discloses the integrated circuit device of claim 1, further comprising: an upper wiring pattern (242+top 241, FIG. 2C) in the peripheral circuit area (PA), the upper wiring pattern (242+top 241) at a second vertical level that is farther from the substrate (201) than a vertical level of the uppermost surface of the capacitor structure (230), wherein the upper wiring pattern (242+top 241) passes through the peripheral protective insulating liner (217P+239) and is connected to the middle wiring pattern (lower 241, FIG. 2C).
Regarding claim 8, Hwang discloses the integrated circuit device of claim 1, further comprising: an inter-wiring insulating film (237, FIG. 2C) in the peripheral circuit area (PA), the inter-wiring insulating film (237) between the plurality of lower wiring patterns (238) and the middle wiring pattern (241), wherein the peripheral protective insulating liner (217P+239) continuously extends from above the surface of the middle wiring pattern (238) to above a top surface of the inter-wiring insulating film (237) to contact the top surface of the inter-wiring insulating film (237, FIG. 2C).
Regarding claim 9, Hwang discloses the integrated circuit device of claim 1, wherein each of the cell protective insulating liner (218) and the peripheral protective insulating liner (217P+239) comprises a silicon boron nitride (SiBN) film, a silicon nitride (SiN) film, a silicon carbonitride (SiCN) film, or a combination thereof (¶ [0035]).
Regarding claim 10, Hwang discloses an integrated circuit device (see Hwang, FIGs. 2A-2C and 11) comprising:
a substrate (201, FIG. 2A) having a cell array area (CA, FIG. 11) and a peripheral circuit area (PA, FIG. 11) including a core area (13P, FIG. 11), the peripheral circuit area (PA) adjacent to the cell array area (CA);
a bit line (212, FIG. 2A) on the substrate (201) in the cell array area (CA);
a cell contact plug (215, FIG. 2A) apart from the bit line (212) in a lateral direction in the cell array area (CA), the cell contact plugs (215) being connected to a cell active area of the substrate (201);
a conductive landing pad (216, FIG. 2A) contacting the cell contact plug (215), the conductive landing pad (216) on the cell contact plug (215) in the cell array area (CA), the conductive landing pad (216) being at a reference vertical level on the substrate (201, FIGs. 2A-2C and 11);
an isolated insulating pattern (217, FIG. 2A) in the cell array area (CA), the isolated insulating pattern (217) covering sidewalls of the conductive landing pad (216, FIG. 2A);
a plurality of lower wiring patterns (238, FIG. 2C) in the peripheral circuit area (PA), the plurality of lower wiring patterns (238) at the reference vertical level (FIGs. 2A-2C and 11);
a capacitor structure (230, FIG. 2A) in the cell array area (CA), the capacitor structure (230) including a lower electrode (220, ¶ [0029]) connected to the conductive landing pad (216, FIG. 2A);
a plurality of middle wiring patterns (241, FIG. 2C) in the peripheral circuit area (PA), the plurality of middle wiring patterns (241) at a first vertical level that is farther from the substrate (201) than the reference vertical level and closer to the substrate (201) than a vertical level of an uppermost surface of the capacitor structure (230), the plurality of middle wiring patterns (241) being apart from each other in the lateral direction (FIGs. 2C and 11);
a cell protective insulating liner (218, FIG. 2A) covering a top surface of each of the conductive landing pad (216) and the isolated insulating pattern (217, FIG. 2A); and
a peripheral protective insulating liner (217P+239, FIG .2C) covering a surface of each of the plurality of middle wiring patterns (241),
wherein at least a portion of the peripheral protective insulating liner (217P+239) has a thickness greater than a thickness of the cell protective insulating liner (218, FIGs. 2A and 2C).
Regarding claim 11, Hwang discloses the integrated circuit device of claim 10, further comprising: an upper wiring pattern (242+top 241, FIG. 2C) in the peripheral circuit area (PA), the upper wiring pattern (242+top 241) at a second vertical level that is farther from the substrate (201) than the vertical level of the uppermost surface of the capacitor structure (230); and an upper contact plug (242) extending in a vertical direction between a selected one of the plurality of middle wiring patterns (lower 241) and the upper wiring pattern (top 241), the upper contact plug (242) contacting each of the upper wiring pattern (top 241) and the middle wiring patterns (lower 241), wherein, in the cell array area (CA), the lower electrode (220) passes through the cell protective insulating liner (218) in the vertical direction and contacts the conductive landing pad (216), and, in the peripheral circuit area (PA), the upper contact plug (242+top 241) passes through the peripheral protective insulating liner (217P+239) in the vertical direction and contacts the selected one of the plurality of middle wiring patterns (lower 241, FIG. 2C).
Regarding claim 12, Hwang discloses the integrated circuit device of claim 10, wherein the cell protective insulating liner (218) has a single layer structure comprising a single insulating liner (218), and the peripheral protective insulating liner (217P+239) includes a first insulating liner (217P) and a second insulating liner (239), which are sequentially stacked on a surface of each of the plurality of middle wiring patterns (lower 241), wherein each of the cell protective insulating liner (218), the first insulating liner (217P), and the second insulating liner (239) includes a silicon boron nitride (SiBN) film, a silicon nitride (SiN) film, a silicon carbonitride (SiCN) film, or a combination thereof (¶ [0035]).
Regarding claim 13, Hwang discloses the integrated circuit device of claim 10, wherein the peripheral protective insulating liner (217P+239) comprises: a first insulating liner (217P) contacting a top surface and sidewalls of each of the plurality of middle wiring patterns (lower 241); and a second insulating liner (239) covering the top surface and the sidewalls of each of the plurality of middle wiring patterns (lower 241), the second insulating liner (239) being apart from the middle wiring patterns (lower 241) with the first insulating liner (217P) between the second insulating liner (239) and the middle wiring patterns (lower 241, FIG. 2C).
Regarding claim 14, Hwang discloses the integrated circuit device of claim 10, wherein the peripheral protective insulating liner (217P+239) comprises: a first insulating liner (217P) contacting a top surface of each of the plurality of middle wiring patterns (241); and a second insulating liner (239) covering the top surface and sidewalls of the plurality of middle wiring patterns (241), the second insulating liner (239) being apart from the top surface of each of the plurality of middle wiring patterns (241) with the first insulating liner (217P) between the second insulating pattern (239) and the top surface of each of the plurality of middle wiring patterns (241), and the second insulating liner (239) contacting the sidewalls of each of the plurality of middle wiring patterns (241, FIG. 2C).
Regarding claim 16, Hwang discloses an integrated circuit device (see Hwang, FIGs. 2A-2C and 11) comprising:
a substrate (201, FIG. 2A) having a cell array area (CA, FIG. 11) and a peripheral circuit area (PA, FIG. 11) including a core area (13P, FIG. 11), the peripheral circuit area (PA) adjacent to the cell array area (CA);
a bit line (212, FIG. 2A) on the substrate (201) in the cell array area (CA);
a cell contact plug (215, FIG. 2A) apart from the bit line (212) in a lateral direction in the cell array area (CA), the cell contact plug (215) being connected to a cell active area of the substrate (201);
a conductive landing pad (216, FIG. 2A) contacting the cell contact plug (215), the conductive landing pad (216) on the cell contact plug (215) in the cell array area (CA), the conductive landing pad (216) being arranged at a reference vertical level on the substrate (201, FIGs. 2A-2C and 11);
an isolated insulating pattern (217, FIG. 2A) in the cell array area (CA), the isolated insulating pattern (217) surrounding sidewalls of the conductive landing pad (216);
a cell protective insulating liner (218, FIG. 2A) in the cell array area (CA), the cell protective insulating liner (218) covering a top surface of each of the conductive landing pad (216) and the isolated insulating pattern (217, FIG. 2A);
a capacitor structure (230, FIG. 2A) including a lower electrode (220, ¶ [0029]), a dielectric film (221, FIG. 2A), and an upper electrode (222, FIG. 2A) in the cell array area (CA), the lower electrode (220) passing through the cell protective insulating liner (218) and contacting the conductive landing pad (216), the dielectric film (221) contacting the lower electrode (220) and the cell protective insulating liner (218), the upper electrode (222) covering the lower electrode (220) with the dielectric film (221) between the upper electrode (222) and the lower electrode (220, FIG. 2A);
a plurality of lower wiring patterns (238, FIG. 2C) in the peripheral circuit area (PA), the plurality of lower wiring patterns (238) at the reference vertical level (FIGs. 2A-2C and 11);
a middle wiring pattern (241, FIG. 2C) in the peripheral circuit area (PA), the middle wiring pattern (241) at a first vertical level, which is farther from the substrate (201) than the reference vertical level and closer to the substrate (201) than a vertical level of an uppermost surface of the upper electrode (222, FIG. 2A);
a peripheral protective insulating liner (217P+239, FIG. 2C) in the peripheral circuit area (PA), the peripheral protective insulating liner (217P+239) covering a surface of the middle wiring pattern (241, FIG. 2C);
an upper wiring pattern (242+top 241, FIG. 2C) at a second vertical level, the second vertical level is farther from the substrate (201) than the vertical level of the uppermost surface of the upper electrode (222) in the peripheral circuit area (PA); and
an upper contact plug (242+top 241) extending in a vertical direction between the middle wiring pattern (lower 241) and the upper wiring pattern (242+top 241), the upper contact plug (242+top 241) passing through the peripheral protective insulating liner (217P+239) and contacting the middle wiring pattern (lower 241), wherein
at least a portion of the peripheral protective insulating liner (217P+239) has a thickness greater than a thickness of the cell protective insulating liner (218, FIGs. 2A and 2C).
Regarding claim 17, Hwang discloses the integrated circuit device of claim 16, wherein the cell protective insulating liner (218) has a single layer structure including a single insulating liner (218), the peripheral protective insulating liner (217P+239) includes a first insulating liner (217P) and a second insulating liner (239) which are sequentially stacked on a surface of the middle wiring pattern (lower 241), and wherein each of the cell protective insulating liner (218), the first insulating liner (217P), and the second insulating liner (239) comprises a silicon boron nitride (SiBN) film, a silicon nitride (SiN) film, a silicon carbonitride (SiCN) film, or a combination thereof (¶ [0035]).
Regarding claim 18, Hwang discloses the integrated circuit device of claim 16, wherein the peripheral protective insulating liner (217P+239) comprises: a first insulating liner (217P) contacting a top surface and sidewalls of the middle wiring pattern (lower 241); and a second insulating liner (239) covering the top surface and the sidewalls of the middle wiring pattern (lower 241), the second insulating liner (239) being apart from the middle wiring pattern (lower 241) with the first insulating liner (217P) between the second insulating liner (239) and the middle wiring pattern (lower 241, FIG. 2C).
Regarding claim 19, Hwang discloses the integrated circuit device of claim 16, wherein the peripheral protective insulating liner (217P+241) comprises: a first insulating liner (217P) contacting a top surface of the middle wiring pattern (241); and a second insulating liner (239) covering the top surface and sidewalls of the middle wiring pattern (241), the second insulating liner (239) being apart from the top surface of the middle wiring pattern (241) with the first insulating liner (217P) between the second insulating liner (239) and the middle wiring pattern (241), and the second insulating liner (239) contacting the sidewalls of the middle wiring pattern (241).
Allowable Subject Matter
Claims 15 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art of record neither anticipates nor renders obvious all the claimed subject of claim 15, in particular, an inter-wiring insulating film in the peripheral circuit area, the inter-wiring insulating film between the plurality of lower wiring patterns and the plurality of middle wiring patterns, wherein the inter-wiring insulating film includes a plurality of recessed top surfaces each being between two adjacent ones of the plurality of middle wiring patterns, the peripheral protective insulating liner includes a plurality of curved portions that respectively conformally contact the plurality of recessed top surfaces of the inter-wiring insulating film and convexly extend toward the substrate.
The prior art of record neither anticipates nor renders obvious all the claimed subject of claim 20, in particular, an inter-wiring insulating film between the plurality of lower wiring patterns and the middle wiring pattern in the peripheral circuit area, wherein the inter-wiring insulating film comprises a pair of recessed top surfaces on both sides of the middle wiring pattern, and the peripheral protective insulating liner comprises a pair of curved portions conformally contacting the pair of recessed top surfaces of the inter-wiring insulating film and convexly extending toward the substrate.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to XIA L. CROSS whose telephone number is (571)270-3273. The examiner can normally be reached 9 am-5:30 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at 571-272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/XIA L CROSS/Primary Examiner, Art Unit 2892
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