DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending in this application.
Response to Amendment
Claims 1, 3, 7, 8, 9, and 16 are amended.
Response to Arguments
Applicant's arguments filed 06/29/2026 have been fully considered but they are not persuasive. Applicant argues that Chen U.S. Patent Application 2020/0294994 (hereinafter “Chen”) teaches that the clamp transistor 26 and MOS transistor 25 form a thyristor structure and as such do not teach the surge protection circuit configured to increase an output capacitance of a high electron mobility transistor by connecting an output capacitor between the drain and the source when a surge occurs. However, the clamp transistor 26 of figure 2 of Chen is connected as a capacitor by connecting the drain, source, and body together (as evidenced by Chiu et al. “Metal-layer capacitors in the 65 nm CMOS process and the application for low-leakage power-rail ESD clamp circuit” (hereinafter “Chiu”) in table 4(a)). During normal operation, the MOS transistor is off, thereby disconnecting clamp transistor 26 and during an ESD event, MOS transistor is turned on, thereby connecting clamp transistor across the terminals of the circuit to be protected (i.e. the HEMT). By connecting the clamp transistor across the terminals of the circuit to be protected, the capacitance of the clamp transistor (i.e. output capacitor) is added to the capacitance of the HEMT, thereby increasing the output capacitance of the HEMT. Therefore, the arguments are not persuasive.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-3, and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wurfl et al. U.S. Patent Application 2013/0240894 (hereinafter “Wurfl”) and further in view of Chen et al. U.S. Patent Application 2020/0294994 (hereinafter “Chen”).
Regarding claim 1, Wurfl teaches a semiconductor device (refer to abstract and figure 1), comprising: a high electron mobility transistor (i.e. compound semiconductor field effect transistor 80)(fig.1)(refer also to [0015]) including a gate (i.e. G)(fig.1) configured to receive a gate signal (i.e. Vgs)(fig.1), a drain (i.e. D)(fig.1) connected to a first terminal (implicit), and a source (i.e. S)(fig.1) connected to a second terminal (implicit); and a surge protection circuit (i.e. ESDD 70)(fig.1); however, Wurfl does not teach the surge protection circuit configured to increase an output capacitance of the high electron mobility transistor by connecting an output capacitor between the drain and the source when a surge occurs, based on a voltage between the drain and the source. However, Chen teaches the surge protection circuit configured to increase an output capacitance of the high electron mobility transistor (refer to clamp transistor 26 and MOS transistor 25)(fig.7)(refer also to [0058]) by connecting an output capacitor between the drain and the source when a surge occurs (refer to [0033]), based on a voltage between the drain and the source (implicit)(refer to second resistor 72 and second capacitor 71)(fig.7). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Wurfl to include the surge protection circuit of Chen to provide the advantage of preventing leakage current in the discharge path when there is no overvoltage (refer to Chen [0058]).
Regarding claim 2, Wurfl and Chen teach the semiconductor device of claim 1, wherein the surge protection circuit includes: a voltage divider circuit (i.e. Chen second capacitor 71 and second resistor 72)(fig.7) connected between the drain and the source (implicit)(refer to Wurfl ESDD 70)(fig.1) and configured to output a dividing voltage that divides the voltage (implicit); a digitizer circuit (refer to Chen transistors 73 and 74)(fig.7)(refer also to Chen [0075]) configured to output at least one of a first voltage or a second voltage lower than the first voltage based on the dividing voltage divided by the voltage divider circuit (implicit); and a protection circuit (i.e. Chen clamp transistor 26 and MOS transistor 25)(fig.7) connected between the drain and the source (implicit)(refer to Wurfl ESDD 70)(fig.1) and configured to change the output capacitance based on the at least one of the first voltage or the second voltage that is output by the digitizer circuit (implicit).
Regarding claim 3, Wurfl and Chen teach the semiconductor device of claim 2, wherein the protection circuit includes: the output capacitor (i.e. Chen clamp transistor 26)(fig.7)(refer also to Chen [0058]) and a first transistor (i.e. Chen MOS transistor 25)(fig.7) connected in series (implicit) between the drain and the source of the high electron mobility transistor (implicit)(refer to Wurfl ESDD 70)(fig.1), and the first transistor includes a gate configured to receive the at least one of the first voltage or the second voltage output by the digitizer circuit (implicit).
Regarding claim 6, Wurfl and Chen teach the semiconductor device of claim 2, wherein the digitizer circuit includes a plurality of inverter circuits (refer to Chen transistors 73 and 74)(fig.7)(refer also to Chen [0071] and [0075]) connected between an output terminal of the voltage divider circuit and an input terminal of the protection circuit (implicit).
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wurfl and Chen as applied to claim 2 above, and further in view of Wu et al. U.S. Patent No. 6,552,886 (hereinafter “Wu”).
Regarding claim 4, Wurfl and Chen teach the semiconductor device of claim 2; however, they do not teach wherein the voltage divider circuit includes at least one of first and second resistors connected in series between the drain and the source of the high electron mobility transistor, or first and second capacitors connected in series between the drain and the source of the high electron mobility transistor. However, Wu teaches wherein the voltage divider circuit includes at least one of first and second resistors (i.e. resistors 24 and 25)(fig.4) connected in series between the drain and the source of the high electron mobility transistor, or first and second capacitors (i.e. filter transistors 26 and 27)(fig.4)(refer also to col. 5 lines 10-16) connected in series between the drain and the source of the high electron mobility transistor (implicit). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Wurfl and Chen to include the voltage divider of Wu to provide the advantage of preventing false triggering of the surge protection circuit (refer to Wu col. 5 lines 10-16).
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wurfl and Chen as applied to claim 6 above, and further in view of Miller et al. U.S. Patent No. 5,946,177 (hereinafter “Miller”).
Regarding claim 7, Wurfl and Chen teach the semiconductor device of claim 6; however, they do not teach wherein plurality of inverter circuits includes: a first transistor connected between the output terminal and a first node configured to be at the second voltage and including a gate connected to the input terminal; and a first resistor connected between the output terminal and a second node configured to be at the first voltage. However, Miller teaches wherein plurality of inverter circuits includes: a first transistor (i.e. transistor 228)(fig.6) connected between the output terminal and a first node configured to be at the second voltage (implicit) and including a gate connected to the input terminal (implicit); and a first resistor (i.e. resistor 231)(fig.6) connected between the output terminal and a second node configured to be at the first voltage (implicit). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Wurfl and Chen to include the inverter of Miller to provide the advantage of properly driving the clamp transistor of the protection circuit.
Claim(s) 16-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kinzer U.S. Patent Application 2016/0049786 (hereinafter “Kinzer”) and further in view of Wurfl and Chen.
Regarding claim 16, Kinzer teaches a power semiconductor system (refer to fig.7), comprising: a switch controller configured to receive a first driving voltage (i.e. VCC)(fig.7), a second driving voltage (i.e. Ground)(fig.7), and a control signal (i.e. input)(fig.7), and to output a gate signal (refer to gate signal in the figure below)(fig.7) based on the first driving voltage, the second driving voltage, and the control signal (implicit); and a power block (i.e. power block in the figure below)(fig.7) including a high electron mobility transistor (i.e. power transistor 110)(fig.7) connected between a first power supply voltage (refer to drain)(fig.7) and a second power supply voltage (refer to ground)(fig.7) configured to be at a level lower than the first power supply voltage (implicit), and configured to receive the gate signal as an input (implicit) and a surge protection circuit (refer to overvoltage protection circuit 705)(fig.7); however, Kinzer does not teach the surge protection circuit connected between a source and a drain of the high electron mobility transistor, and configured to increase an output capacitance of the high electron mobility transistor by connecting an output capacitor between the drain and the source when a surge occurs. However, Wurfl teaches the surge protection circuit (i.e. ESDD 70)(fig.1) connected between a source and a drain of the high electron mobility transistor (i.e. compound semiconductor field effect transistor 80)(fig.1)(refer also to [0015]); however, Kinzer and Wurfl do not teach the surge protection circuit configured to increase an output capacitance of the high electron mobility transistor by connecting an output capacitor between the drain and the source when a surge occurs. However, Chen teaches the surge protection circuit configured to increase an output capacitance of the high electron mobility transistor (refer to clamp transistor 26 and MOS transistor 25)(fig.7)(refer also to [0058]) by connecting an output capacitor between the drain and the source when a surge occurs (refer to [0033]). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the power semiconductor device of Kinzer and Wurfl to include the surge protection circuit of Chen to provide the advantage of preventing leakage current in the discharge path when there is no overvoltage (refer to Chen [0058]).
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Regarding claim 17, Kinzer, Wurfl, and Chen teach the power semiconductor system of claim 16, wherein the surge protection circuit includes: a first transistor (i.e. Chen MOS transistor 25)(fig.7) including a gate (implicit) configured to receive a voltage corresponding to a voltage difference between the source and the drain of the high electron mobility transistor (implicit)(refer to Chen resistor 72, capacitor 71, and transistors 73 and 74)(fig.7); and an output capacitor (i.e. Chen clamp transistor 26)(fig.7) including one electrode connected to the drain of the high electron mobility transistor (implicit) and another electrode connected to the drain of the first transistor (implicit).
Regarding claim 18, Kinzer, Wurfl, and Chen teach the power semiconductor system of claim 17, wherein the surge protection circuit further includes: a voltage divider circuit (i.e. Chen resistor 72 and capacitor 71)(fig.7) configured to divide a voltage difference between the source and the drain (implicit); and a digitizer circuit (i.e. Chen transistors 73 and 74)(fig.7) configured to output a first voltage and a second voltage lower than the first voltage based on the voltage divided by the voltage divider circuit (implicit), and the first transistor configured to turn on in response to the first voltage being applied and to turn off in response to the second voltage being applied (implicit).
Regarding claim 19, Kinzer, Wurfl, and Chen teach the power semiconductor system of claim 18, wherein the digitizer circuit is further configured to output the first voltage in response to the voltage distributed by the voltage division circuit exceeding a threshold voltage (implicit), and to output the second voltage in response to the voltage divided by the voltage divider circuit being less than the threshold voltage (implicit).
Regarding claim 20, Kinzer, Wurfl, and Chen teach the power semiconductor system of claim 16, wherein: the switch controller includes a gate driver (i.e. Kinzer high side transistor 710 and low side transistor 745)(fig.7) configured to output the first driving voltage to turn on the high electron mobility transistor or the second driving voltage to turn off the high electron mobility transistor, based on the control signal (implicit).
Claim(s) 1/are rejected under 35 U.S.C. 103 as being unpatentable over Wurfl and further in view of Sugimoto Japanese Patent Document JP H05-111150 A (hereinafter “Sugimoto”).
Regarding claim 1, Wurfl teaches a semiconductor device (refer to abstract and figure 1), comprising: a high electron mobility transistor (i.e. compound semiconductor field effect transistor 80)(fig.1)(refer also to [0015]) including a gate (i.e. G)(fig.1) configured to receive a gate signal (i.e. Vgs)(fig.1), a drain (i.e. D)(fig.1) connected to a first terminal (implicit), and a source (i.e. S)(fig.1) connected to a second terminal (implicit); and a surge protection circuit (i.e. ESDD 70)(fig.1); however, Wurfl does not teach the surge protection circuit configured to increase an output capacitance of the high electron mobility transistor by connecting an output capacitor between the drain and the source when a surge occurs, based on a voltage between the drain and the source. However, Sugimoto teaches the surge protection circuit configured to increase an output capacitance of the high electron mobility transistor (refer to transistor 6 and capacitor 4)(fig.1)(refer also to Abstract) by connecting an output capacitor (i.e. capacitor 4)(fig.1) between the drain and the source when a surge occurs (refer to abstract), based on a voltage between the drain and the source (implicit)(refer to abstract). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Wurfl to include the surge protection circuit of Chen to provide the advantage of preventing leakage current in the discharge path when there is no overvoltage.
Claim(s) 2, 3, and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wurfl and Sugimoto as applied to claim 1 above, and further in view of Chen.
Regarding claim 2, Wurfl and Sugimoto teach the semiconductor device of claim 1, wherein the surge protection circuit includes: a voltage divider circuit (i.e. Sugimoto capacitor 8 and resistor 9)(fig.1) connected between the drain and the source (implicit)(refer to Wurfl ESDD 70)(fig.1) and configured to output a dividing voltage that divides the voltage (implicit); and a protection circuit (i.e. Sugimoto transistor 6 and capacitor 4)(fig.1) connected between the drain and the source (implicit)(refer to Wurfl ESDD 70)(fig.1) and configured to change the output capacitance (implicit); however, they do not teach a digitizer circuit configured to output at least one of a first voltage or a second voltage lower than the first voltage based on the dividing voltage divided by the voltage divider circuit; the protection circuit configured to change the capacitance based on the at least one of the first voltage or the second voltage that is output by the digitizer circuit (implicit). However, Chen teaches a digitizer circuit (refer to Chen transistors 73 and 74)(fig.7)(refer also to Chen [0075]) configured to output at least one of a first voltage or a second voltage lower than the first voltage based on the dividing voltage divided by the voltage divider circuit (implicit); and the protection circuit (i.e. Chen clamp transistor 26 and MOS transistor 25)(fig.7) configured to change the output capacitance based on the at least one of the first voltage or the second voltage that is output by the digitizer circuit (implicit). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Wurfl and Sugimoto to include the digitizer of Chen to provide the advantage of ensuring full turn on/off of the transistor 6 of Sugimoto.
Regarding claim 3, Wurfl, Sugimoto, and Chen teach the semiconductor device of claim 2, wherein the protection circuit includes: the output capacitor (i.e. Sugimoto capacitor 4)(fig.1) and a first transistor (i.e. Sugimoto transistor 6)(fig.1) connected in series (implicit) between the drain and the source of the high electron mobility transistor (implicit)(refer to Wurfl ESDD 70)(fig.1), and the first transistor includes a gate configured to receive the at least one of the first voltage or the second voltage output by the digitizer circuit (implicit)(refer to Chen MOS transistor 25)(fig.7).
Regarding claim 6, Wurfl, Sugimoto, and Chen teach the semiconductor device of claim 2, wherein the digitizer circuit includes a plurality of inverter circuits (refer to Chen transistors 73 and 74)(fig.7)(refer also to Chen [0071] and [0075]) connected between an output terminal of the voltage divider circuit and an input terminal of the protection circuit (implicit).
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wurfl, Sugimoto, and Chen as applied to claim 2 above, and further in view of Wu et al. U.S. Patent No. 6,552,886 (hereinafter “Wu”).
Regarding claim 4, Wurfl, Sugimoto, and Chen teach the semiconductor device of claim 2; however, they do not teach wherein the voltage divider circuit includes at least one of first and second resistors connected in series between the drain and the source of the high electron mobility transistor, or first and second capacitors connected in series between the drain and the source of the high electron mobility transistor. However, Wu teaches wherein the voltage divider circuit includes at least one of first and second resistors (i.e. resistors 24 and 25)(fig.4) connected in series between the drain and the source of the high electron mobility transistor, or first and second capacitors (i.e. filter transistors 26 and 27)(fig.4)(refer also to col. 5 lines 10-16) connected in series between the drain and the source of the high electron mobility transistor (implicit). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Wurfl, Sugimoto, and Chen to include the voltage divider of Wu to provide the advantage of preventing false triggering of the surge protection circuit (refer to Wu col. 5 lines 10-16).
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wurfl, Sugimoto, and Chen as applied to claim 6 above, and further in view of Miller et al. U.S. Patent No. 5,946,177 (hereinafter “Miller”).
Regarding claim 7, Wurfl, Sugimoto, and Chen teach the semiconductor device of claim 6; however, they do not teach wherein plurality of inverter circuits includes: a first transistor connected between the output terminal and a first node configured to be at the second voltage and including a gate connected to the input terminal; and a first resistor connected between the output terminal and a second node configured to be at the first voltage. However, Miller teaches wherein plurality of inverter circuits includes: a first transistor (i.e. transistor 228)(fig.6) connected between the output terminal and a first node configured to be at the second voltage (implicit) and including a gate connected to the input terminal (implicit); and a first resistor (i.e. resistor 231)(fig.6) connected between the output terminal and a second node configured to be at the first voltage (implicit). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Wurfl, Sugimoto, and Chen to include the inverter of Miller to provide the advantage of properly driving the clamp transistor of the protection circuit.
Claim(s) 16 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kinzer U.S. Patent Application 2016/0049786 (hereinafter “Kinzer”) and further in view of Wurfl and Sugimoto.
Regarding claim 16, Kinzer teaches a power semiconductor system (refer to fig.7), comprising: a switch controller configured to receive a first driving voltage (i.e. VCC)(fig.7), a second driving voltage (i.e. Ground)(fig.7), and a control signal (i.e. input)(fig.7), and to output a gate signal (refer to gate signal in the figure above)(fig.7) based on the first driving voltage, the second driving voltage, and the control signal (implicit); and a power block (i.e. power block in the figure above)(fig.7) including a high electron mobility transistor (i.e. power transistor 110)(fig.7) connected between a first power supply voltage (refer to drain)(fig.7) and a second power supply voltage (refer to ground)(fig.7) configured to be at a level lower than the first power supply voltage (implicit), and configured to receive the gate signal as an input (implicit) and a surge protection circuit (refer to overvoltage protection circuit 705)(fig.7); however, Kinzer does not teach the surge protection circuit connected between a source and a drain of the high electron mobility transistor, and configured to increase an output capacitance of the high electron mobility transistor by connecting an output capacitor between the drain and the source when a surge occurs. However, Wurfl teaches the surge protection circuit (i.e. ESDD 70)(fig.1) connected between a source and a drain of the high electron mobility transistor (i.e. compound semiconductor field effect transistor 80)(fig.1)(refer also to [0015]); however, Kinzer and Wurfl do not teach the surge protection circuit configured to increase an output capacitance of the high electron mobility transistor by connecting an output capacitor between the drain and the source when a surge occurs. However, Sugimoto teaches the surge protection circuit configured to increase an output capacitance of the high electron mobility transistor (refer to capacitor 4 and transistor 6)(fig.1)(refer also to abstract) by connecting an output capacitor (i.e. capacitor 4)(fig.1) between the drain and the source when a surge occurs (refer to abstract). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the power semiconductor device of Kinzer and Wurfl to include the surge protection circuit of Sugimoto to provide the advantage of preventing leakage current in the discharge path when there is no overvoltage.
Regarding claim 20, Kinzer, Wurfl, and Sugimoto teach the power semiconductor system of claim 16, wherein: the switch controller includes a gate driver (i.e. Kinzer high side transistor 710 and low side transistor 745)(fig.7) configured to output the first driving voltage to turn on the high electron mobility transistor or the second driving voltage to turn off the high electron mobility transistor, based on the control signal (implicit).
Claim(s) 17-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kinzer, Wurfl, and Sugimoto as applied to claim 16 above, and further in view of Chen.
Regarding claim 17, Kinzer, Wurfl, and Sugimoto teach the power semiconductor system of claim 16, wherein the surge protection circuit includes: a first transistor (i.e. Sugimoto transistor 6)(fig.1) including a control terminal (implicit) configured to receive a voltage corresponding to a voltage difference between the source and the drain of the high electron mobility transistor (implicit)(refer to Sugimoto resistor 9 and capacitor 8)(fig.1); and an output capacitor (i.e. Sugimoto capacitor 4)(fig.1) including one electrode connected to the drain of the high electron mobility transistor (implicit) and another electrode connected to the first terminal of the first transistor (implicit); however, they do not teach wherein the control terminal is a gate and the first terminal is a drain. However, Chen teaches wherein the control terminal is a gate (refer to MOS transistor 25)(fig.7) and the first terminal is a drain (refer to MOS transistor 25)(fig.7). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Kinzer, Wurfl, and Sugimoto to include the MOS transistor of Chen to provide the advantage of using a common alternative to the BJT transistor of Sugimoto.
Regarding claim 18, Kinzer, Wurfl, Sugimoto, and Chen teach the power semiconductor system of claim 17, wherein the surge protection circuit further includes: a voltage divider circuit (i.e. Sugimoto resistor 9 and capacitor 8)(fig.1) configured to divide a voltage difference between the source and the drain (implicit); and a digitizer circuit (i.e. Chen transistors 73 and 74)(fig.7) configured to output a first voltage and a second voltage lower than the first voltage based on the voltage divided by the voltage divider circuit (implicit), and the first transistor configured to turn on in response to the first voltage being applied and to turn off in response to the second voltage being applied (implicit).
Regarding claim 19, Kinzer, Wurfl, Sugimoto, and Chen teach the power semiconductor system of claim 18, wherein the digitizer circuit is further configured to output the first voltage in response to the voltage distributed by the voltage division circuit exceeding a threshold voltage (implicit), and to output the second voltage in response to the voltage divided by the voltage divider circuit being less than the threshold voltage (implicit).
Allowable Subject Matter
Claims 5 and 8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for the indication of allowable subject matter: Claim 5 is indicated as containing allowable subject matter because prior art fails to teach or suggest, either alone or in combination all of the limitations of claim 5, especially wherein the voltage divider circuit includes a first capacitor and a second capacitor connected in series between the drain and the source of the high electron mobility transistor, and a first transistor connected between one electrode of the second capacitor and another electrode of the second capacitor and having a gate configured to receive the gate signal.
Claim 8 is indicated as containing allowable subject matter because prior art fails to teach or suggest, either alone or in combination all of the limitations of claim 8, especially wherein the plurality of inverter circuits include: a first transistor connected between the output terminal and the first voltage; a second transistor connected between a gate of the first transistor and a first node configured to be at the first voltage and including a gate connected to the first node; a third transistor connected between the output terminal and a second node configured to be at the second voltage and including a gate connected to the input terminal; and a first capacitor connected between the gate of the first transistor and the output terminal.
Claims 9-15 are allowed.
The following is an examiner’s statement of reasons for allowance: Claims 9-15 are allowable because prior art fails to teach or suggest, either alone or in combination all of the limitations of claim 9, especially the first electrode on a first protective layer on the barrier layer, a second protective layer on the first electrode, and the second electrode on the second protective layer. The closest prior art references of record are Wurfl, Shin et al. U.S. Patent Application 2022/0310833 (hereinafter “Shin”), Chen, Wu, Miller, Sugimoto, and Kinzer. Regarding claim 9, Wurfl teaches a power semiconductor device (refer to abstract and figure 1), comprising: a high electron mobility transistor (i.e. compound semiconductor field effect transistor 80)(fig.1)(refer also to [0015]) including a channel layer (refer to active area 29)(fig.5)(refer also to [0015]), a barrier layer (i.e. barrier layer 24)(fig.5)(refer also to [0015]) on the channel layer (implicit)(refer to fig. 5 and [0015]) and including a material having an energy band gap different from that of the channel layer (refer to [0015]), a gate electrode (i.e. gate 28)(fig.5) on the barrier layer (implicit)(refer to fig.5), a source electrode (i.e. source terminal 30)(fig.5) on a first side of the gate electrode (implicit), and a drain electrode (i.e. drain terminal 31)(fig.5) on a second side of the gate electrode (implicit), wherein the source electrode and the drain electrode connected to the channel layer (implicit); however, Wurfl does not teach a gate semiconductor layer between the barrier layer and the gate electrode; a first capacitor including a first electrode on a first protective layer on the barrier layer, a second protective layer on the first electrode, and a second electrode on the second protective layer; and a first transistor connecting the first capacitor between the drain electrode and the source electrode, the connecting based on a voltage between the drain electrode and the source electrode. However, Shin teaches a gate semiconductor layer (i.e. p-type semiconductor layer 40)(fig.1A) between the barrier layer and the gate electrode (implicit). However, Wurfl and Shin do not teach a first capacitor including a first electrode on a first protective layer on the barrier layer, a second protective layer on the first electrode, and a second electrode on the second protective layer; and a first transistor connecting the first capacitor between the drain electrode and the source electrode, the connecting based on a voltage between the drain electrode and the source electrode. However, Chen teaches a first capacitor (i.e. clamp transistor 26)(fig.7) including a first electrode (implicit) and a second electrode (implicit); and a first transistor (i.e. MOS transistor 25)(fig.7) connecting the first capacitor between the drain electrode and the source electrode (implicit), the connecting based on a voltage between the drain electrode and the source electrode (implicit); however, Chen does not teach the first electrode on a first protective layer on the barrier layer, a second protective layer on the first electrode, and the second electrode on the second protective layer. Wu (figure 4), Miller (figure 6), Sugimoto (figure 1) and Kinzer (figure 7) teach similar devices; however they do not teach the first electrode on a first protective layer on the barrier layer, a second protective layer on the first electrode, and the second electrode on the second protective layer. It would not have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the power semiconductor device of Wurfl, Shin, Chen, Wu, Miller, Sugimoto, and/or Kinzer to arrive at the claimed invention. Claims 10-15 are allowed based on their dependency on claim 9.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
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/KEVIN J COMBER/Primary Examiner, Art Unit 2838
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