Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Claims 1-3 and 5-9 set forth in the amendment submitted 6/29/2026 form the basis of the present examination.
Response to Arguments
The objection to the specification (Abstract), set forth to the Non-Final Office action mailed on 3/27/2026 has been withdrawn because of the amendment filed on 6/29/2026.
Applicant’s arguments, see remarks page 6, filed 6/29/2026, with respect to the rejection(s) of Claims 1-10 under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention have been fully considered as follows:
Applicant’s Argument:
Applicant argues on page 6, of the remarks, filed on 6/29/2026, regarding the rejection(s) of Claims 1-10 under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention, that “The Examiner has rejected claims 1-10 under 35 U.S.C. §112, second paragraph as being indefinite.
Applicant respectfully submits that the rejection of claims 1-10 is overcome by the accompanying amendment thereto.”
Examiner Response:
Applicant’s arguments, see remarks page 6 (stated above), filed 6/29/2026, with respect to the rejection(s) of Claims 1-10 under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention, as applied to the Non-Final office Action mailed on 3/27/2026 have been fully considered and is persuasive. Because applicant has amended the claims and added the limitation which makes the claim clear. Therefore the rejection of Claims 1-10 under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention, as applied to the Non-Final office Action mailed on 3/27/2026 has been withdrawn as set forth below.
Applicant’s arguments, see remarks page 6-10, filed 6/29/2026, with respect to the rejection(s) of Claim(s) 1-4 and 7-10 under 35 U.S.C. 102 (a) (1) as being anticipated by BANG in the US Patent Application Publication Number US 20190288619 A1 and the rejection of Claim(s) 5-6 under 35 U.S.C. 103 as being unpatentable over BANG ‘619 A1 in view of SHINOHARA in the US Patent Application Publication Number US 20130249452 A1, have been fully considered as follows:
Applicant’s Argument:
Applicant argues on page 7-9, of the remarks, filed on 6/29/2026, regarding the rejection(s) of Claim(s) 1-4 and 7-10 under 35 U.S.C. 102 (a) (1) as being anticipated by BANG in the US Patent Application Publication Number US 20190288619 A1 and the rejection of Claim(s) 5-6 under 35 U.S.C. 103 as being unpatentable over BANG ‘619 A1 in view of SHINOHARA in the US Patent Application Publication Number US 20130249452 A1, that “Applicant respectfully submits that Bang, Shinohara, taken individually or combined, fail to teach or suggest inventive features of the presently claimed invention, wherein the processor is further configured to synchronize a phase of the command signal and a phase of the resolver signal by delaying output of the command signal for the compensation time, as is called for by claim(s) 1 and 7……………..
However, Applicant respectfully disagrees because Bang merely discloses the excitation signal which is a fixed input signal and corresponds to a reference signal for detecting a reception delay time of the resolver. See Bang, paragraphs 0071 and 0101, as recited below.
Accordingly, Bang merely controls the resolver signal (Remarks-Page 7).
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In contrast, Applicant's independent claims 1 and 7 call for inventive features of the presently claimed invention, wherein the processor is further configured to synchronize a phase of the command signal and a phase of the resolver signal by delaying output of the command signal for the compensation time. See Application, FIGS. 2 and 4, reproduced below; and paragraphs 0039-0040.
In this configuration, the compensation module (340) of the present invention may synchronize a phase of the command signal and a phase of the resolver signal by controlling an output timing of the command signal output from the microcomputer (21) such that the command signal is output after the compensation time (tcp) has elapsed from a time point at which the command signal is received. See id.
Accordingly, the present invention may effectively compensate for a phase delay of a resolver signal, which are capable of compensating for the phase delay of the resolver signal by (Remarks-Page 8) synchronizing a phase of the command signal and a phase of the resolver signal by delaying output of the command signal for the compensation time.
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For at least these reasons, Applicant respectfully submits that Bang and Shinohara do neither anticipate nor render obvious independent claims 1 and 7 (Remarks-Page 9).”
Examiner Response:
Applicant’s arguments, see remarks page 7-9 (stated above), filed 6/29/2026, with respect to the rejection(s) of Claim(s) 1-4 and 7-10 under 35 U.S.C. 102 (a) (1) as being anticipated by BANG in the US Patent Application Publication Number US 20190288619 A1 and the rejection of Claim(s) 5-6 under 35 U.S.C. 103 as being unpatentable over BANG ‘619 A1 in view of SHINOHARA in the US Patent Application Publication Number US 20130249452 A1, as applied to the Non-Final Office Action mailed on 3/27/2026 have been fully considered and is persuasive. Because applicant has amended the claims and added the limitation in claim 1, “an input/output interface configured to receive a command signal and a resolver signal; and a processor connected to the input/output interface, wherein the processor comprises: a delay time calculation module configured to calculate a delay time of the resolver signal with respect to the command signal; a compensation time calculation module configured to calculate a compensation time based on the delay time; and a compensation module configured to control an output timing of the command signal such that the command signal is output after the compensation time has elapsed from a time point at which the command signal is received, wherein the processor is further configured to synchronize a phase of the command signal and a phase of the resolver signal by delaying output of the command signal for the compensation time” which necessitates a new ground of rejection because claim now requires a compensation module configured to control an output timing of the command signal such that the command signal is output after the compensation time has elapsed from a time point at which the command signal is received. Bang does not disclose a compensation module configured to control an output timing of the command signal. Therefore, the present amendment changes the scope of the claim which necessities a new ground of rejection and overcomes the present rejection of claim 1 under 35 U.S.C. 102 (a) (1) as being anticipated by BANG in the US Patent Application Publication Number US 20190288619 A1 and the rejection of Claim(s) 5-6 under 35 U.S.C. 103 as being unpatentable over BANG ‘619 A1 in view of SHINOHARA in the US Patent Application Publication Number US 20130249452 A1, as applied to the Non-Final Office Action mailed on 3/27/2026 and the rejection has been withdrawn. Therefore, the rejection has been withdrawn. Bai et al. (Hereinafter, “Bai”) in the US patent Application Publication Number US 20090190705 A1 is applied to meet at least the amended limitation of claim 1. Therefore claim 1 is now rejected under 35 U.S.C. 103 as being unpatentable over BANG in the US Patent Application Publication Number US 20190288619 A1 in view of Bai et al. (Hereinafter, “Bai”) in the US Patent Application Publication Number US 20090190705 A1, as set forth below.
Similarly, Independent claim 7 is now rejected under 35 U.S.C. 103 as being unpatentable over BANG in the US Patent Application Publication Number US 20190288619 A1 in view of Bai et al. (Hereinafter, “Bai”) in the US Patent Application Publication Number US 20090190705 A1, as set forth below, because of the same reason as stated for claim 1 because claim 13 has similar amendment to independent claim 1 as explained above. Applicant’s argument is moot in view of newly applied combination of references. See the rejection set forth below.
Dependent claims 2-3 and 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over BANG in the US Patent Application Publication Number US 20190288619 A1 in view of Bai et al. (Hereinafter, “Bai”) in the US Patent Application Publication Number US 20090190705 A1 and Claim(s) 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over BANG ‘619 A1 in view of Bai et al. (Hereinafter, “Bai”) in the US Patent Application Publication Number US 20090190705 A1 and further in view of SHINOHARA in the US Patent Application Publication Number US 20130249452 A1, as set forth below because of the same reason as stated above. See the rejection set forth below.
For expedite prosecution Applicant is invited to call to discuss the present rejection also if any further clarification needed and to discuss any possible amendment to overcome the references to make the claims allowable.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3 and 7-9 are rejected under 35 U.S.C. 103 as being unpatentable over BANG in the US Patent Application Publication Number US 20190288619 A1 in view of Bai et al. (Hereinafter, “Bai”) in the US Patent Application Publication Number US 20090190705 A1.
Regarding claim 1, Bang teaches an apparatus for compensating for a phase delay of a resolver signal (A resolver management device which precisely measures a delay time, a resolver system including the same, and an operating method thereof; Paragraph [0006] Line 2-4; FIG. 1 is a diagram illustrating an example of a resolver system 10; Paragraph [0050] Line 1-2; The resolver management device 200 may measure a delay time of a phase detection of the resolver sensor; Paragraph [0102] Line 1-4), the apparatus [10] comprising:
an input/output interface [200] (resolver management device 200 as the input/ output interface) (Referring to FIG. 1, the resolver system 10 may include a resolver sensor 100, a resolver management device 200, and a micro controller unit (MCU) 300; Paragraph [0051] Line 1-3; Figure 1: Modified Figure 1 of Bang below shows an input/output interface 200) configured to receive a command signal (excitation signal as the command signal) and a resolver signal (a reflected excitation signal as the resolver signal) (The resolver management device 200 may be implemented so as to measure a delay time between an excitation signal applied from the resolver management device 200 to the resolver sensor 100 and a reflected excitation signal output through the resolver sensor 100, and compensate for and diagnose the delay time; Paragraph [0054] Line 1-6; Figure 1: Modified Figure 1 of Bang below shows processor receive a command signal (excitation signal as the command signal) and a resolver signal (a reflected excitation signal as the resolver signal) through the input/output interface [200]); and
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Figure 1: Modified Figure 1 of Bang
a processor [300] (MCU 300 as the processor) (Referring to FIG. 1, the resolver system 10 may include a resolver sensor 100, a resolver management device 200, and a micro controller unit (MCU) 300; Paragraph [0051] Line 1-3) connected to the input/output interface [200] (In the exemplary embodiment, the resolver management device 200 and the MCU 300 may be mounted on one board; Paragraph [0051] Line 3-5),
wherein the processor [300] comprises:
a delay time calculation module [300] (The MCU 300 may calculate a delay time of the resolver sensor 100 based on the count information; Paragraph [0066] Line 1-2; The MCU 300 may be implemented so as to control a general operation of the resolver system 10. Although not illustrated, the MCU 300 may include a square wave generator, an analog-digital converter, and a calculation unit; Paragraph [0076] Line 1-5) configured to calculate a delay time of the resolver signal with respect to the command signal (The delay information management device 250 may be implemented so as to store a first count value related to the first delay time, a second count value related to the second delay time, and a count value related to a period of a control signal, and to transmit the stored count information to the MCU 300; Paragraph [0065] Line 1-6; The MCU 300 may calculate a delay time of the resolver sensor 100 based on the count information; Paragraph [0066] Line 1-2),
a compensation time calculation module [300] (calculation unit as the compensation time calculation module) configured to calculate a compensation time based on the delay time (In the exemplary embodiment of the present invention, the resolver system 10 may be implemented so as to measure/compensate for a delay time generable by a position within a vehicle between the resolver management device 200 controlling the resolver sensor 100 and the resolver sensor, the kind of resolver, and hardware; Paragraph [0079] Line 1-6; The resolver management device 200 may be implemented so as to measure a delay time between an excitation signal applied from the resolver management device 200 to the resolver sensor 100 and a reflected excitation signal output through the resolver sensor 100, and compensate for and diagnose the delay time; Paragraph [0054] Line 1-6; The calculation unit may be implemented so as to receive the delay time information (for example, the internal clock count value) from the delay information management device 250, and calculate the degree of correction of the excitation signal corresponding to the delay time information; Paragraph [0078] Line 1-6; The MCU 300 may be implemented so as to control a general operation of the resolver system 10. Although not illustrated, the MCU 300 may include a square wave generator, an analog-digital converter, and a calculation unit; Paragraph [0076] Line 1-5; Therefore, the calculation unit of the MCU receive the delay information and calculate the degree of correction which represent delay the command signal by the compensation time; MCU calculate a relative time by providing the reference signal and predetermined internal delay time information together and estimates the directly provided external resolver driving signal time);
wherein the processor [300] is further configured to synchronize a phase of the command signal and a phase of the resolver signal (In the exemplary embodiment, when the delay time is less than the threshold value, the delay detecting circuit may transmit the delay time information to the MCU 300. In this case, the MCU 300 may synchronize the excitation signal and the output signal of the resolver sensor 100 by correcting the excitation signal input to the resolver sensor 100 in accordance with the delay time information; Paragraph [0071] Line 1-7; The resolver management device 200 may be implemented so as to measure a delay time between an excitation signal applied from the resolver management device 200 to the resolver sensor 100 and a reflected excitation signal output through the resolver sensor 100, and compensate for and diagnose the delay time; Paragraph [0054] Line 1-6).
However, Bang fails to teach a compensation module configured to control an output timing of the command signal such that the command signal is output after the compensation time has elapsed from a time point at which the command signal is received and the processor is further configured to synchronize a phase of the command signal and a phase of the resolver signal by delaying output of the command signal for the compensation time
Bai teaches a way to determine and compensate the delay between the in-phase and the quadrature-phase components of a communication signal (Paragraph [0003] Line 1-4),
a compensation module [Figure 6] configured to control an output timing (The signal t.sub.I0 on connection 622 and the signal t.sub.Q0) of the command signal (The signal t.sub.IQ is used to compensate for the I/Q signal delay by altering the term I.sub.rx(t-t.sub.0)+jQ.sub.rx(t-t.sub.0) to account for I/Q signal delay) uch that the command signal is output after the compensation time has elapsed from a time point at which the command signal is received (FIG. 6 is a schematic diagram illustrating an alternative embodiment of the system and method for in-phase/quadrature-phase (I/Q) time delay measurement. In an embodiment, the system and method for in-phase/quadrature-phase (I/Q) time delay measurement can be implemented using a conventional synchronizer, such that the I/Q delay measurement results can be used for compensation of I/Q time delay in a baseband demodulator, such as the baseband demodulator 420 of FIG. 4; Paragraph [0032] Line 1-9; In the embodiment shown in FIG. 6, the in-phase component, I.sub.rx(t), of the receive signal is supplied to a synchronizer 606 via connection 602 and the quadrature-phase component, Q.sub.rx(t), of the receive signal is supplied to a synchronizer 606 via connection 604. The output of the synchronizer 606 is the complex term I.sub.rx(t-t.sub.0)+jQ.sub.rx(t-t.sub.0). However, the term I.sub.rx(t-t.sub.0)+jQ.sub.rx(t-t.sub.0) fails to account for any time delay between the in-phase component and the quadrature-phase component. The output of the synchronizer 606 is supplied via connection 618 to a baseband demodulator 628; Paragraph [0033] Line 1-10) and the processor is further configured to synchronize a phase of the signal by delaying output of the command signal for the compensation time (In the embodiment shown in FIG. 6, the in-phase component, I.sub.rx(t), of the receive signal is supplied to a synchronizer 606 via connection 602 and the quadrature-phase component, Q.sub.rx(t), of the receive signal is supplied to a synchronizer 606 via connection 604. The output of the synchronizer 606 is the complex term I.sub.rx(t-t.sub.0)+jQ.sub.rx(t-t.sub.0). However, the term I.sub.rx(t-t.sub.0)+jQ.sub.rx(t-t.sub.0) fails to account for any time delay between the in-phase component and the quadrature-phase component. The output of the synchronizer 606 is supplied via connection 618 to a baseband demodulator 628; Paragraph [0033] Line 1-10; The output of the start time determination module 612 is a signal, t.sub.Q0, representing the start time of the quadrature-phase component of the receive signal, Q.sub.rx(t). The signal t.sub.I0 on connection 622 and the signal t.sub.Q0 on connection 624 are supplied to a subtractor 626. The output of the subtractor 626 is a signal, t.sub.IQ, representing the net delay of the in-phase and the quadrature-phase receive signals. The signal t.sub.IQ is supplied via connection 632 to the baseband demodulator 628. The signal t.sub.IQ is used to compensate for the I/Q signal delay by altering the term I.sub.rx(t-t.sub.0)+jQ.sub.rx(t-t.sub.0) to account for I/Q signal delay; Paragraph [0037] Line 1-11). The purpose of doing so is to compensate for the delay, to determine and compensate the delay between the in-phase and the quadrature-phase components of a communication signal.
It would have obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, to modify Bang in view of Bai, because Bai teaches to include a compensation module to control an output timing of the command signal compensates for the delay (Paragraph [0019]), determines and compensate the delay between the in-phase and the quadrature-phase components of a communication signal (Paragraph [0003]).
Regarding claim 2, Bang teaches an apparatus,
wherein the processor [300] is configured to calculate the delay time (an actual EXC driving delay time is the delay time in response to an elapse preset time as the time interval from one point (for example, a point corresponding to the rising edge of the external control signal) of the excitation signal generated from the excitation signal generator 210 (see FIG. 1) to any one pole) in response to an elapse of a preset time (the time interval from one point (for example, a point corresponding to the rising edge of the external control signal) of the excitation signal generated from the excitation signal generator 210 (see FIG. 1) to any one pole as the preset time) that is calculated from a time point at which a motor (In the exemplary embodiment of the present invention, the resolver system 10 may be implemented so as to measure/compensate for a delay time generable by a position within a vehicle between the resolver management device 200 controlling the resolver sensor 100 and the resolver sensor, the kind of resolver, and hardware; Paragraph [0079] Line 1-6) is driven (The first delay detector 230 (see FIG. 1) may count a time interval from one point (for example, a point corresponding to the rising edge of the external control signal) of the excitation signal generated from the excitation signal generator 210 (see FIG. 1) to any one pole and generate a first count value D1; Paragraph [0084] Line 1-6; Herein, the first count value D1 is a value corresponding to an actual EXC driving delay time; Paragraph [0085] Line 1-2; The resolver management device 200 may accurately measure each of a driving delay time that is a time interval from a reception time of the control signal to a generation time of the excitation signal and a reception delay time that is a time interval from an output time of the excitation signal to the resolver sensor 100 (see FIG. 1) to a reception time of the reflected excitation signal; Paragraph [0090] Line 1-7).
Regarding claim 3, Bang teaches an apparatus,
wherein the processor [300] further comprises a frequency detection module (The resolver management device 200 according to the exemplary embodiment of the present invention may set the number of frequency counters transmitted from the outside as a reference, and then separate and accurately measure a delay time up to the generation of a frequency, a processing delay time of a reflected signal, and the like; Paragraph [0103] Line 1-6; When an internal frequency is changed, the number of relative counters may be changed as a reference. Accordingly, the resolver management device 200 (see FIG. 1) may provide the MCU 300 with information about the delay time to the external signal without a frequency synchronization circuit; Paragraph [0089] Line 1-6) configured to: detect a frequency of the command signal (Herein, the excitation signal may be a sine wave signal having a predetermined frequency. In the exemplary embodiment, the excitation signal generator 210 may include a square wave-sine wave converter; Paragraph [0057] Line 1-4; According to the resolver management device, the resolver system including the same, and the method of operating the same according to the exemplary embodiment of the present invention, it is possible to set the number of frequency counters transmitted from the outside as a reference, and then separate and accurately measure a delay time up to the generation of a frequency, a processing delay time of a reflected signal, and the like; Paragraph [0030] Line 1-8) calculate a period of the command signal (excitation signal) based on the detected frequency (According to the resolver management device, the resolver system including the same, and the method of operating the same according to the exemplary embodiment of the present invention, it is possible to set the number of frequency counters transmitted from the outside as a reference, and then separate and accurately measure a delay time up to the generation of a frequency, a processing delay time of a reflected signal, and the like; Paragraph [0030] Line 1-8; The resolver signal receiver 220 may be implemented so as to receive the excitation signal (for example, a sine wave signal or a cosine wave signal) reflected from the resolver sensor 100; Paragraph [0058] Line 1-4), and
calculate, as the compensation time, a value by subtracting the delay time from the calculated period of the command signal (The first delay detector 230 may be implemented so as to detect a first delay time between the control signal of the square wave received from the MCU 300 and the excitation signal of the sine wave generated in the excitation signal generator 210. Herein, the first delay time may be referred to as a driving delay time; Paragraph [0059] Line 1-6; The second delay detector 240 may be implemented so as to detect a second delay time between the excitation signal output to the resolver sensor 100 and the reflected excitation signal received from the resolver sensor 100. Herein, the second delay time may be referred to as a reception delay time; Paragraph [0062] Line 1-6; The delay information management device 250 may be implemented so as to store a first count value related to the first delay time, a second count value related to the second delay time, and a count value related to a period of a control signal, and to transmit the stored count information to the MCU 300; Paragraph [0065] Line 1-6; For example, the delay information management device 250 may calculate a count value corresponding to a delay time of the resolver sensor 100 by subtracting the first count value corresponding to the first delay time from the second count value corresponding to the second delay time; Paragraph [0068] Line; The resolver management device 200 may be implemented so as to measure a delay time between an excitation signal applied from the resolver management device 200 to the resolver sensor 100 and a reflected excitation signal output through the resolver sensor 100, and compensate for and diagnose the delay time; Paragraph [0054] Line 1-6; By calculating the first count value and second count value and by subtracting the values compensation time is calculated).
Regarding claim 7, Bang teaches a method of compensating for a phase delay of a resolver signal (A resolver management device which precisely measures a delay time, a resolver system including the same, and an operating method thereof; Paragraph [0006] Line 2-4; FIG. 1 is a diagram illustrating an example of a resolver system 10; Paragraph [0050] Line 1-2; The resolver management device 200 may measure a delay time of a phase detection of the resolver sensor; Paragraph [0102] Line 1-4) which is performed in a computing device including a processor [300] (MCU 300 as the processor) (Referring to FIG. 1, the resolver system 10 may include a resolver sensor 100, a resolver management device 200, and a micro controller unit (MCU) 300; Paragraph [0051] Line 1-3) (Depending on an exemplary embodiment, a part or all of the steps and/or the operations may be implemented or performed by using one or more processors driving a command stored in one or more non-temporary computer-readable media, a program, an interactive data structure, a client, and/or a server. An example of the one or more non-temporary computer-readable media may be software, firmware, hardware, and/or any combination thereof; Paragraph [0141] Line 1-8), the method comprising:
receiving a command signal (excitation signal as the command signal) and a resolver signal (a reflected excitation signal as the resolver signal) (The resolver management device 200 may be implemented so as to measure a delay time between an excitation signal applied from the resolver management device 200 to the resolver sensor 100 and a reflected excitation signal output through the resolver sensor 100, and compensate for and diagnose the delay time; Paragraph [0054] Line 1-6; Figure 1: Modified Figure 1 of Bang above shows processor receive a command signal (excitation signal as the command signal) and a resolver signal (a reflected excitation signal as the resolver signal) through the input/output interface [200]),
calculating a delay time of the resolver signal with respect to the command signal based on the command signal and the resolver signal (The delay information management device 250 may be implemented so as to store a first count value related to the first delay time, a second count value related to the second delay time, and a count value related to a period of a control signal, and to transmit the stored count information to the MCU 300; Paragraph [0065] Line 1-6; The MCU 300 may calculate a delay time of the resolver sensor 100 based on the count information; Paragraph [0066] Line 1-2),
calculating a compensation time based on the delay time (In the exemplary embodiment of the present invention, the resolver system 10 may be implemented so as to measure/compensate for a delay time generable by a position within a vehicle between the resolver management device 200 controlling the resolver sensor 100 and the resolver sensor, the kind of resolver, and hardware; Paragraph [0079] Line 1-6; The resolver management device 200 may be implemented so as to measure a delay time between an excitation signal applied from the resolver management device 200 to the resolver sensor 100 and a reflected excitation signal output through the resolver sensor 100, and compensate for and diagnose the delay time; Paragraph [0054] Line 1-6), and
delaying output of the command signal by the compensation time (In the exemplary embodiment, when the period of the external driving signal is changed, a reference time change may be updated. In the exemplary embodiment, a high-rank determining block (for example, the MCU) may calculate a relative time by providing the reference signal and predetermined internal delay time information together. In the exemplary embodiment, the high-rank determining block counter-estimates the directly provided external resolver driving signal time, thereby accurately determining an absolute time; Paragraph [0101] Line 1-10; The calculation unit may be implemented so as to receive the delay time information (for example, the internal clock count value) from the delay information management device 250, and calculate the degree of correction of the excitation signal corresponding to the delay time information; Paragraph [0078] Line 1-6; The MCU 300 may be implemented so as to control a general operation of the resolver system 10. Although not illustrated, the MCU 300 may include a square wave generator, an analog-digital converter, and a calculation unit; Paragraph [0076] Line 1-5; Therefore, the calculation unit of the MCU receive the delay information and calculate the degree of correction which represent delay the command signal by the compensation time; MCU calculate a relative time by providing the reference signal and predetermined internal delay time information together and estimates the directly provided external resolver driving signal time).
However, Bang fails to teach controlling an output timing of the command signal such that the command signal is output after the compensation time has elapsed, wherein controlling the output timing of the command signal by the compensation time results in a synchronizing of a phase of the command signal and a phase of the resolver signal.
Bai teaches a way to determine and compensate the delay between the in-phase and the quadrature-phase components of a communication signal (Paragraph [0003] Line 1-4),
controlling an output timing of the command signal (The signal t.sub.I0 on connection 622 and the signal t.sub.Q0) of the command signal (The signal t.sub.IQ is used to compensate for the I/Q signal delay by altering the term I.sub.rx(t-t.sub.0)+jQ.sub.rx(t-t.sub.0) to account for I/Q signal delay) such that the command signal is output after the compensation time has elapsed (FIG. 6 is a schematic diagram illustrating an alternative embodiment of the system and method for in-phase/quadrature-phase (I/Q) time delay measurement. In an embodiment, the system and method for in-phase/quadrature-phase (I/Q) time delay measurement can be implemented using a conventional synchronizer, such that the I/Q delay measurement results can be used for compensation of I/Q time delay in a baseband demodulator, such as the baseband demodulator 420 of FIG. 4; Paragraph [0032] Line 1-9; In the embodiment shown in FIG. 6, the in-phase component, I.sub.rx(t), of the receive signal is supplied to a synchronizer 606 via connection 602 and the quadrature-phase component, Q.sub.rx(t), of the receive signal is supplied to a synchronizer 606 via connection 604. The output of the synchronizer 606 is the complex term I.sub.rx(t-t.sub.0)+jQ.sub.rx(t-t.sub.0). However, the term I.sub.rx(t-t.sub.0)+jQ.sub.rx(t-t.sub.0) fails to account for any time delay between the in-phase component and the quadrature-phase component. The output of the synchronizer 606 is supplied via connection 618 to a baseband demodulator 628; Paragraph [0033] Line 1-10); wherein controlling the output timing of the command signal by the compensation time results in a synchronizing of a phase of the command signal and a phase of the resolver signal (In the embodiment shown in FIG. 6, the in-phase component, I.sub.rx(t), of the receive signal is supplied to a synchronizer 606 via connection 602 and the quadrature-phase component, Q.sub.rx(t), of the receive signal is supplied to a synchronizer 606 via connection 604. The output of the synchronizer 606 is the complex term I.sub.rx(t-t.sub.0)+jQ.sub.rx(t-t.sub.0). However, the term I.sub.rx(t-t.sub.0)+jQ.sub.rx(t-t.sub.0) fails to account for any time delay between the in-phase component and the quadrature-phase component. The output of the synchronizer 606 is supplied via connection 618 to a baseband demodulator 628; Paragraph [0033] Line 1-10; The output of the start time determination module 612 is a signal, t.sub.Q0, representing the start time of the quadrature-phase component of the receive signal, Q.sub.rx(t). The signal t.sub.I0 on connection 622 and the signal t.sub.Q0 on connection 624 are supplied to a subtractor 626. The output of the subtractor 626 is a signal, t.sub.IQ, representing the net delay of the in-phase and the quadrature-phase receive signals. The signal t.sub.IQ is supplied via connection 632 to the baseband demodulator 628. The signal t.sub.IQ is used to compensate for the I/Q signal delay by altering the term I.sub.rx(t-t.sub.0)+jQ.sub.rx(t-t.sub.0) to account for I/Q signal delay; Paragraph [0037] Line 1-11). The purpose of doing so is to compensate for the delay, to determine and compensate the delay between the in-phase and the quadrature-phase components of a communication signal.
It would have obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, to modify Bang in view of Bai, because Bai teaches to control an output timing of the command signal compensates for the delay (Paragraph [0019]), determines and compensate the delay between the in-phase and the quadrature-phase components of a communication signal (Paragraph [0003]).
Regarding claim 8, Bang teaches a method,
wherein the calculating of the delay time includes calculating the delay time (an actual EXC driving delay time is the delay time in response to an elapse preset time as the time interval from one point (for example, a point corresponding to the rising edge of the external control signal) of the excitation signal generated from the excitation signal generator 210 (see FIG. 1) to any one pole) in response to an elapse of a preset time (the time interval from one point (for example, a point corresponding to the rising edge of the external control signal) of the excitation signal generated from the excitation signal generator 210 (see FIG. 1) to any one pole as the preset time) calculated from a time point at which a motor (In the exemplary embodiment of the present invention, the resolver system 10 may be implemented so as to measure/compensate for a delay time generable by a position within a vehicle between the resolver management device 200 controlling the resolver sensor 100 and the resolver sensor, the kind of resolver, and hardware; Paragraph [0079] Line 1-6) is driven (The first delay detector 230 (see FIG. 1) may count a time interval from one point (for example, a point corresponding to the rising edge of the external control signal) of the excitation signal generated from the excitation signal generator 210 (see FIG. 1) to any one pole and generate a first count value D1; Paragraph [0084] Line 1-6; Herein, the first count value D1 is a value corresponding to an actual EXC driving delay time; Paragraph [0085] Line 1-2; The resolver management device 200 may accurately measure each of a driving delay time that is a time interval from a reception time of the control signal to a generation time of the excitation signal and a reception delay time that is a time interval from an output time of the excitation signal to the resolver sensor 100 (see FIG. 1) to a reception time of the reflected excitation signal; Paragraph [0090] Line 1-7).
Regarding claim 9, Bang teaches a method,
wherein the calculating of the compensation time further includes:
detecting a frequency of the command signal (Herein, the excitation signal may be a sine wave signal having a predetermined frequency. In the exemplary embodiment, the excitation signal generator 210 may include a square wave-sine wave converter; Paragraph [0057] Line 1-4; According to the resolver management device, the resolver system including the same, and the method of operating the same according to the exemplary embodiment of the present invention, it is possible to set the number of frequency counters transmitted from the outside as a reference, and then separate and accurately measure a delay time up to the generation of a frequency, a processing delay time of a reflected signal, and the like; Paragraph [0030] Line 1-8),
calculating a period of the command signal (excitation signal) based on the detected frequency (According to the resolver management device, the resolver system including the same, and the method of operating the same according to the exemplary embodiment of the present invention, it is possible to set the number of frequency counters transmitted from the outside as a reference, and then separate and accurately measure a delay time up to the generation of a frequency, a processing delay time of a reflected signal, and the like; Paragraph [0030] Line 1-8; The resolver signal receiver 220 may be implemented so as to receive the excitation signal (for example, a sine wave signal or a cosine wave signal) reflected from the resolver sensor 100; Paragraph [0058] Line 1-4), and
calculating, as the compensation time, a value obtained by subtracting the delay time from the calculated period as the compensation time (The first delay detector 230 may be implemented so as to detect a first delay time between the control signal of the square wave received from the MCU 300 and the excitation signal of the sine wave generated in the excitation signal generator 210. Herein, the first delay time may be referred to as a driving delay time; Paragraph [0059] Line 1-6; The second delay detector 240 may be implemented so as to detect a second delay time between the excitation signal output to the resolver sensor 100 and the reflected excitation signal received from the resolver sensor 100. Herein, the second delay time may be referred to as a reception delay time; Paragraph [0062] Line 1-6; The delay information management device 250 may be implemented so as to store a first count value related to the first delay time, a second count value related to the second delay time, and a count value related to a period of a control signal, and to transmit the stored count information to the MCU 300; Paragraph [0065] Line 1-6; For example, the delay information management device 250 may calculate a count value corresponding to a delay time of the resolver sensor 100 by subtracting the first count value corresponding to the first delay time from the second count value corresponding to the second delay time; Paragraph [0068] Line; The resolver management device 200 may be implemented so as to measure a delay time between an excitation signal applied from the resolver management device 200 to the resolver sensor 100 and a reflected excitation signal output through the resolver sensor 100, and compensate for and diagnose the delay time; Paragraph [0054] Line 1-6; By calculating the first count value and second count value and by subtracting the values compensation time is calculated).
Claim(s) 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over BANG ‘619 A1 in view of Bai ‘705 A1, as applied to claim 1 above, and further in view of SHINOHARA in the US Patent Application Publication Number US 20130249452 A1.
Regarding claim 5, Bang teaches an apparatus,
wherein the compensation time calculation module comprises:
a comparison module [a first comparator 232-1, a second comparator 232-2, . . . ], configured to compare the resolver signal with a preset reference voltage (first threshold and second threshold value) and output a corresponding comparison result (a pole of the excitation signal as the comparison result) (FIG. 3 is a diagram illustrating an example of the first delay detector 230 according to the exemplary embodiment of the present invention. Referring to FIG. 3, the first delay detector 230 may include a first comparator 232-1, a second comparator 232-2, . . . , and an i.sup.th comparator 232-i (i is a natural number equal to or larger than 2), and a first delay measuring device 234; Paragraph [0104] Line 1-7; The first comparator 232-1 may be implemented so as to output a first threshold value; Paragraph [0105] Line 1-2; The second comparator 232-2 may be implemented so as to output a second threshold value. Herein, the second threshold value may be larger than the first threshold value; The first delay measuring device 234 detects a pole of the excitation signal generated by the excitation signal generator 210 by using the first threshold value, the second threshold value, . . . , and the i.sup.th threshold value; Paragraph [0107] Line 1-4),
an edge detection module [234] (delay measuring device 234 as the edge detection module as it detect rising edge) configured to detect an edge (a rising edge) in a signal from an output signal of the comparison result and output a corresponding edge detection result (a count value of the internal clock as a first delay time) (The first delay measuring device 234 may be implemented so as to count a time interval from a point corresponding to a predetermined point (for example, a rising edge) of an external control signal to the detected pole by using an internal clock, and output a count value of the internal clock as a first delay time; Paragraph [0108] Line 1-6).
However, the combination of Bang and Bai fails to teach that a filter module configured to filter one or more signals for a rising edge and a falling edge included in a signal of an edge detection result and calculate the delay time of the resolver signal with respect to the command signal based on a signal for a filtering result and the command signal.
Shinohara teaches an angle detector comprising: an AD converter configured to analog-to-digital convert plural-phase signal waves having respective different phases; a corrector configured to delay a phase of an excitation signal by an amount corresponding to a phase difference between the excitation signal and the signal wave (abstract), wherein
a filter module configured to filter (first high pass filter 27 in Figure 2) one or more signals (The AD conversion section 22 includes a first .DELTA..SIGMA. AD converter 26, a first HPF (high pass filter) 27, and a first multiplier 28. The first .DELTA..SIGMA. AD converter 26 converts the analog sin phase signal and outputs a discrete sin phase signal. The first HPF 27 passes a high-frequency component of a signal output from the .DELTA..SIGMA. AD converter 26. The first multiplier 28 multiplies the output signal from the HPF 27 and the rotation angle .theta. input from the angle calculating section 25; Paragraph [0041] Line 1-8) for a rising edge and a falling edge included in a signal of an edge detection result (A phase delay time measurement section 46 (detecting section) measures a phase delay time DT. The phase delay time measurement section 46 detects the phase of the square sum average signal at the zero cross timing, and the phase shift amount is obtained; Paragraph [0132] Line 1-5; As shown in FIGS. 5 and 14A, the phase delay time measurement section 46 includes another zero-point detecting section 46a which detects the zero-cross point of the square sum average signal from an output of the adder 40 (FIG. 5) and a counter 46b which receives an input of a detection signal from the zero-point detecting section 46a and the input of the excitation signal RS from the port 202 (FIG. 5). The phase delay time measurement section 46 starts counting by a counter 46b from a timing of rising of the excitation signal RS. The phase delay time measurement section 46 stops the counter 46b from counting by a detection signal in the rising timing or a detection signal in the falling timing; Paragraph [0133] line 1-13), and
calculate the delay time of the resolver signal with respect to the command signal based on a signal for a filtering result and the command signal (The excitation signal generator 20 has an exciter which outputs an excitation wave, an amplifier which amplifies the output of the exciter, and a comparator which limits an amplitude level of an amplified and output excitation wave. The excitation signal generator 20 inputs the excitation signal sin .omega.t output from the exciter to the excitation coil 19. The excitation signal generator 20 inputs the excitation signal output from the comparator to the resolver digital convertor 10; Paragraph [0032] Line 1-8; The phase correction unit 23 of FIG. 2 delays the phase of the excitation signal RS. The delay amount according to the phase correction unit 23 is DT (see, FIG. 3D). The delay amount DT is a phase delay (phase difference) between phases of two-phase signal waves and a phase of the excitation signal; Paragraph [0050] Line 1-6). The purpose of doing so is to detect the phase shift amount with high accuracy, to perform synchronous detection to an output signal from the AD converter in synchronization with the excitation signal whose phase is corrected; and an angle calculator configured to calculate an estimated rotation angle using an output signal of the wave detector and output the estimated rotation angle to the AD converter.
It would have obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, to modify Bang and Bai by including a filter to filter one or more signals for a rising edge and a falling edge included in a signal of an edge detection result as disclosed by Shinohara, because Shinohara teaches to filter one or more signals for a rising edge and a falling edge included in a signal of an edge detection result detects the phase shift amount with high accuracy (Paragraph [0136]), performs synchronous detection to an output signal from the AD converter in synchronization with the excitation signal whose phase is corrected; and an angle calculator configured to calculate an estimated rotation angle using an output signal of the wave detector and output the estimated rotation angle to the AD converter (paragraph [0023]).
Regarding claim 6, the combination of Bang and Bai fails to teach an apparatus, wherein the processor is configured to identify a type of an edge first detected within a period of the command signal and determine the one or more signals to be filtered according to the identified type.
Shinohara teaches an angle detector comprising: an AD converter configured to analog-to-digital convert plural-phase signal waves having respective different phases; a corrector configured to delay a phase of an excitation signal by an amount corresponding to a phase difference between the excitation signal and the signal wave (abstract), wherein
the processor is configured to identify a type of an edge first detected within a period of the command signal and determine the one or more signals to be filtered according to the identified type (FIG. 10C is a view showing an output signal example of the comparator 59. The timing of zero-cross detection by the rising detecting section 43 corresponds to a positive edge clock of a signal from Low to High; Paragraph [0074] Line 1-4; The configuration of the falling detecting section 44 is substantially the same as the configuration of the rising detecting section 43. The timing of zero-cross detection by the falling detecting section 44 corresponds to a negative edge clock of a signal from High to Low. The operation start timing of the falling detecting section 44 is different from the operation start timing of the rising detecting section 43; Paragraph [0075] Line 1-7; In FIG. 5, the zero-point detecting section 35 includes two phase correction direction output portions 45a and 45b (phase correction direction outputters) on the output side of the rising detecting section 43 and two phase correction direction output portions 45c and 45d on the output side of the falling detecting section 44 (reference numerals 1, 2, 5, and 6 and 3, 4, 7, and 0 will be described later); Paragraph [0076] Line 1-7). The purpose of doing so is to detect the phase shift amount with high accuracy, to perform synchronous detection to an output signal from the AD converter in synchronization with the excitation signal whose phase is corrected; and an angle calculator configured to calculate an estimated rotation angle using an output signal of the wave detector and output the estimated rotation angle to the AD converter.
It would have obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, to modify Bang and Bai by filtering one or more signals for a rising edge and a falling edge included in a signal of an edge detection result as disclosed by Shinohara, because Shinohara teaches to identify a type of an edge first detected within a period of the command signal and determine the one or more signals to be filtered detects the phase shift amount with high accuracy (Paragraph [0136]), performs synchronous detection to an output signal from the AD converter in synchronization with the excitation signal whose phase is corrected; and an angle calculator configured to calculate an estimated rotation angle using an output signal of the wave detector and output the estimated rotation angle to the AD converter (Paragraph [0023]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Lee et al. (US 20210010832 A1) discloses, “METHOD AND APPARATUS FOR MONITORING A RESOLVER-[0005] An aspect of the disclosure includes detecting a fault associated with the resolver based upon the monitoring of the first and second output signals from the resolver at the oversampling rate. [0030] FIG. 1 schematically illustrates details of a resolver 20 that is arranged to monitor a device 10 having a rotatable member 12. In one embodiment, the device 110 is an electric motor 10, and the rotatable member 12 is a rotor 12 that is disposed in a stator 14 and couples to a load (not shown). Rotational position of the rotor 12 is monitored by the resolver 20, which is coupled to a controller 40 via an interface circuit 50. Operation of the device 10, including rotational speed and/or position of the rotor 12, is controlled via a motor controller (not shown). The resolver 20 may be disposed in a location for monitoring rotational position and/or rotation speed of the rotor 12. The load may be, by way of a non-limiting example, a gear box coupled to a drive wheel that interacts with a ground surface when employed as part of a powertrain system for a ground vehicle. The concepts described within may apply to various configurations of a resolver 20 that is arranged to determine rotational position and/or speed of a rotatable member 12 of a device 10. [0031] The resolver 20 includes a resolver rotor 22 that fixedly attaches to the rotor 12, and a resolver stator 24 that attaches to a grounding element, e.g., the device 10. The resolver rotor 22 includes a primary electrical winding referred to herein as an excitation winding 23, and the resolver stator 24 includes two secondary electrical windings referred to herein as first and second secondary windings 25, 27, respectively. Alternatively, the resolver 20 may be a variable reluctance resolver having the excitation winding 23 and the first and second secondary windings 25, 27 disposed on the resolver stator 24, wherein rotation of the resolver rotor 22 modulates an airgap therebetween to generate output signals in the form of first and second secondary signals 26, 28 on the first and second secondary windings 25, 27. [0038] FIG. 2, with continued reference to FIG. 1, schematically illustrates the oversampling routine 200 for evaluating an output signal from an embodiment of the resolver 20 that is coupled to a rotatable member, to advantageously detect a resolver-related fault over a range of rotational speeds-However Lee does not disclose a compensation module configured to control an output timing of the command signal such that the command signal is output after the compensation time has elapsed from a time point at which the command signal is received, wherein the processor is further configured to synchronize a phase of the command signal and a phase of the resolver signal by delaying output of the command signal for the compensation time.”
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NASIMA MONSUR whose telephone number is (571)272-8497. The examiner can normally be reached 10:00 am-6:00 pm.
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/NASIMA MONSUR/Primary Examiner, Art Unit 2858
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